| Message ID | 20221116123505.2760397-1-abel.vesa@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] dt-bindings: PCI: qcom: Add SM8550 to binding | expand |
On 16/11/2022 13:35, Abel Vesa wrote: > Add the SM8550 platform to the binding. Subject: Drop redundant, second "binding" > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 96 +++++++++++++++++++ > 1 file changed, 96 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 54f07852d279..efa01a8411c4 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -34,6 +34,8 @@ properties: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550-pcie0 > + - qcom,pcie-sm8550-pcie1 I am not sure what's the benefit of encoding arbitrary IDs to compatible just to differentiate by clocks. The devices are basically the same, so compatible should be the same. > - qcom,pcie-ipq6018 > > reg: > @@ -92,6 +94,10 @@ properties: > power-domains: > maxItems: 1 > > + enable-gpios: > + description: GPIO controlled connection to ENABLE# signal > + maxItems: 1 Does not look like used property... > + > perst-gpios: > description: GPIO controlled connection to PERST# signal > maxItems: 1 > @@ -187,6 +193,8 @@ allOf: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550-pcie0 > + - qcom,pcie-sm8550-pcie1 > then: > properties: > reg: > @@ -601,6 +609,92 @@ allOf: > items: > - const: pci # PCIe core reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sm8550-pcie0 > + then: > + properties: > + clocks: > + minItems: 11 > + maxItems: 11 > + clock-names: > + items: > + - const: pipe # PIPE clock > + - const: pipe_mux # PIPE MUX > + - const: phy_pipe # PIPE output clock > + - const: ref # REFERENCE clock > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: aggre0 # Aggre NoC PCIe0 AXI clock > + interconnects: > + maxItems: 1 > + interconnect-names: > + const: icc_path Keep existing pattern of allOf:if:then or change entire file to a different style. Best regards, Krzysztof
On Wed, Nov 16, 2022 at 02:35:04PM +0200, Abel Vesa wrote: > Add the SM8550 platform to the binding. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 96 +++++++++++++++++++ > 1 file changed, 96 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 54f07852d279..efa01a8411c4 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -34,6 +34,8 @@ properties: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550-pcie0 > + - qcom,pcie-sm8550-pcie1 You should only need one compatible even if there are differences in which bus clocks you need to enable. > - qcom,pcie-ipq6018 > > reg: > @@ -92,6 +94,10 @@ properties: > power-domains: > maxItems: 1 > > + enable-gpios: > + description: GPIO controlled connection to ENABLE# signal > + maxItems: 1 > + > perst-gpios: > description: GPIO controlled connection to PERST# signal > maxItems: 1 > @@ -187,6 +193,8 @@ allOf: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550-pcie0 > + - qcom,pcie-sm8550-pcie1 > then: > properties: > reg: > @@ -601,6 +609,92 @@ allOf: > items: > - const: pci # PCIe core reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sm8550-pcie0 > + then: > + properties: > + clocks: > + minItems: 11 > + maxItems: 11 > + clock-names: > + items: > + - const: pipe # PIPE clock > + - const: pipe_mux # PIPE MUX > + - const: phy_pipe # PIPE output clock The mux and pipe output does not belong in the binding and instead the muxing should be handled by the clock driver (cf. sc8280xp). You can probably drop the refclock too. > + - const: ref # REFERENCE clock > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: aggre0 # Aggre NoC PCIe0 AXI clock Johan
Hi Abel, On 16.11.22 14:35, Abel Vesa wrote: > Add the SM8550 platform to the binding. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 96 +++++++++++++++++++ > 1 file changed, 96 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 54f07852d279..efa01a8411c4 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -34,6 +34,8 @@ properties: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550-pcie0 > + - qcom,pcie-sm8550-pcie1 > - qcom,pcie-ipq6018 > > reg: > @@ -92,6 +94,10 @@ properties: > power-domains: > maxItems: 1 > > + enable-gpios: > + description: GPIO controlled connection to ENABLE# signal > + maxItems: 1 > + > perst-gpios: > description: GPIO controlled connection to PERST# signal > maxItems: 1 > @@ -187,6 +193,8 @@ allOf: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550-pcie0 > + - qcom,pcie-sm8550-pcie1 > then: > properties: > reg: > @@ -601,6 +609,92 @@ allOf: > items: > - const: pci # PCIe core reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sm8550-pcie0 > + then: > + properties: > + clocks: > + minItems: 11 > + maxItems: 11 > + clock-names: > + items: > + - const: pipe # PIPE clock > + - const: pipe_mux # PIPE MUX > + - const: phy_pipe # PIPE output clock > + - const: ref # REFERENCE clock > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: aggre0 # Aggre NoC PCIe0 AXI clock > + interconnects: > + maxItems: 1 > + interconnect-names: > + const: icc_path > + iommus: > + maxItems: 1 > + iommu-map: > + maxItems: 2 > + power-domains: > + maxItems: 1 > + power-domain-names: > + const: gdsc > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: pci # PCIe core reset > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sm8550-pcie1 > + then: > + properties: > + clocks: > + minItems: 12 > + maxItems: 12 > + clock-names: > + items: > + - const: pipe # PIPE clock > + - const: pipe_mux # PIPE MUX > + - const: phy_pipe # PIPE output clock > + - const: ref # REFERENCE clock > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: aggre1 # Aggre NoC PCIe1 AXI clock > + - const: cnoc_pcie_sf_axi # Config NoC PCIe1 AXI clock > + interconnects: > + maxItems: 1 > + interconnect-names: > + const: icc_path The name of the path is too generic. Probably something like "pcie-mem" or "pcie-ddr" would be more appropriate to indicate that this is for requesting bandwidth on the path between PCIE and DDR memory. Thanks, Georgi > + iommus: > + maxItems: 1 > + iommu-map: > + maxItems: 2 > + power-domains: > + maxItems: 1 > + power-domain-names: > + const: gdsc > + resets: > + maxItems: 2 > + reset-names: > + items: > + - const: pci # PCIe core reset > + - const: pcie_1_link_down_reset # PCIe link down reset > + > - if: > properties: > compatible: > @@ -672,6 +766,8 @@ allOf: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550-pcie0 > + - qcom,pcie-sm8550-pcie1 > then: > oneOf: > - properties:
On Wed, 16 Nov 2022 at 14:36, Abel Vesa <abel.vesa@linaro.org> wrote: > > Add the SM8550 platform to the binding. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 96 +++++++++++++++++++ > 1 file changed, 96 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index 54f07852d279..efa01a8411c4 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -34,6 +34,8 @@ properties: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550-pcie0 > + - qcom,pcie-sm8550-pcie1 > - qcom,pcie-ipq6018 > > reg: > @@ -92,6 +94,10 @@ properties: > power-domains: > maxItems: 1 > > + enable-gpios: > + description: GPIO controlled connection to ENABLE# signal > + maxItems: 1 > + > perst-gpios: > description: GPIO controlled connection to PERST# signal > maxItems: 1 > @@ -187,6 +193,8 @@ allOf: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550-pcie0 > + - qcom,pcie-sm8550-pcie1 > then: > properties: > reg: > @@ -601,6 +609,92 @@ allOf: > items: > - const: pci # PCIe core reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sm8550-pcie0 > + then: > + properties: > + clocks: > + minItems: 11 > + maxItems: 11 > + clock-names: > + items: > + - const: pipe # PIPE clock > + - const: pipe_mux # PIPE MUX > + - const: phy_pipe # PIPE output clock > + - const: ref # REFERENCE clock > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: aggre0 # Aggre NoC PCIe0 AXI clock > + interconnects: > + maxItems: 1 > + interconnect-names: > + const: icc_path > + iommus: > + maxItems: 1 > + iommu-map: > + maxItems: 2 > + power-domains: > + maxItems: 1 > + power-domain-names: > + const: gdsc > + resets: > + maxItems: 1 > + reset-names: > + items: > + - const: pci # PCIe core reset > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sm8550-pcie1 > + then: > + properties: > + clocks: > + minItems: 12 > + maxItems: 12 > + clock-names: > + items: > + - const: pipe # PIPE clock > + - const: pipe_mux # PIPE MUX > + - const: phy_pipe # PIPE output clock > + - const: ref # REFERENCE clock You should not need these four clocks. They are unused by the driver. Same applies to pcie0 too. > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: aggre1 # Aggre NoC PCIe1 AXI clock > + - const: cnoc_pcie_sf_axi # Config NoC PCIe1 AXI clock > + interconnects: > + maxItems: 1 > + interconnect-names: > + const: icc_path > + iommus: > + maxItems: 1 > + iommu-map: > + maxItems: 2 > + power-domains: > + maxItems: 1 > + power-domain-names: > + const: gdsc > + resets: > + maxItems: 2 > + reset-names: > + items: > + - const: pci # PCIe core reset > + - const: pcie_1_link_down_reset # PCIe link down reset > + > - if: > properties: > compatible: > @@ -672,6 +766,8 @@ allOf: > - qcom,pcie-sm8250 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550-pcie0 > + - qcom,pcie-sm8550-pcie1 > then: > oneOf: > - properties: > -- > 2.34.1 >
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 54f07852d279..efa01a8411c4 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -34,6 +34,8 @@ properties: - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550-pcie0 + - qcom,pcie-sm8550-pcie1 - qcom,pcie-ipq6018 reg: @@ -92,6 +94,10 @@ properties: power-domains: maxItems: 1 + enable-gpios: + description: GPIO controlled connection to ENABLE# signal + maxItems: 1 + perst-gpios: description: GPIO controlled connection to PERST# signal maxItems: 1 @@ -187,6 +193,8 @@ allOf: - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550-pcie0 + - qcom,pcie-sm8550-pcie1 then: properties: reg: @@ -601,6 +609,92 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8550-pcie0 + then: + properties: + clocks: + minItems: 11 + maxItems: 11 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + interconnects: + maxItems: 1 + interconnect-names: + const: icc_path + iommus: + maxItems: 1 + iommu-map: + maxItems: 2 + power-domains: + maxItems: 1 + power-domain-names: + const: gdsc + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8550-pcie1 + then: + properties: + clocks: + minItems: 12 + maxItems: 12 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + - const: cnoc_pcie_sf_axi # Config NoC PCIe1 AXI clock + interconnects: + maxItems: 1 + interconnect-names: + const: icc_path + iommus: + maxItems: 1 + iommu-map: + maxItems: 2 + power-domains: + maxItems: 1 + power-domain-names: + const: gdsc + resets: + maxItems: 2 + reset-names: + items: + - const: pci # PCIe core reset + - const: pcie_1_link_down_reset # PCIe link down reset + - if: properties: compatible: @@ -672,6 +766,8 @@ allOf: - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 + - qcom,pcie-sm8550-pcie0 + - qcom,pcie-sm8550-pcie1 then: oneOf: - properties:
Add the SM8550 platform to the binding. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- .../devicetree/bindings/pci/qcom,pcie.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+)