| Message ID | 20221027031554.2856036-1-LeoLiu-oc@zhaoxin.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/5] ACPI/APEI: Add apei_hest_parse_aer() | expand |
On Thu, Oct 27, 2022 at 11:15:54AM +0800, LeoLiu-oc wrote: > From: leoliu-oc <leoliu-oc@zhaoxin.com> > > Define PCI Express Advanced Error Reporting Extended Capabilities bits. > > Signed-off-by: leoliu-oc <leoliu-oc@zhaoxin.com> > --- > include/uapi/linux/pci_regs.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 57b8e2ffb1dd..3662106fd8dc 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -799,6 +799,11 @@ > #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ > #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ > > +/* PCI Express Advanced Error Reporting Extended Capabilities for Bridges */ > +#define PCI_ERR_UNCOR_MASK2 0x30 /* Secondary Uncorrectable Error Mask */ > +#define PCI_ERR_UNCOR_SEVER2 0x34 /* Secondary Uncorrectable Error Severit */ > +#define PCI_ERR_CAP2 0x38 /* Secondary Advanced Error Capabilities */ Can you include a spec reference for these? I'm looking at PCIe r6.0, sec 7.8.4, and I don't see anything I can match up with these. Bjorn
在 2022/10/28 5:56, Bjorn Helgaas 写道: > On Thu, Oct 27, 2022 at 11:15:54AM +0800, LeoLiu-oc wrote: >> From: leoliu-oc <leoliu-oc@zhaoxin.com> >> >> Define PCI Express Advanced Error Reporting Extended Capabilities bits. >> >> Signed-off-by: leoliu-oc <leoliu-oc@zhaoxin.com> >> --- >> include/uapi/linux/pci_regs.h | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h >> index 57b8e2ffb1dd..3662106fd8dc 100644 >> --- a/include/uapi/linux/pci_regs.h >> +++ b/include/uapi/linux/pci_regs.h >> @@ -799,6 +799,11 @@ >> #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ >> #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ >> >> +/* PCI Express Advanced Error Reporting Extended Capabilities for Bridges */ >> +#define PCI_ERR_UNCOR_MASK2 0x30 /* Secondary Uncorrectable Error Mask */ >> +#define PCI_ERR_UNCOR_SEVER2 0x34 /* Secondary Uncorrectable Error Severit */ >> +#define PCI_ERR_CAP2 0x38 /* Secondary Advanced Error Capabilities */ > > Can you include a spec reference for these? I'm looking at PCIe r6.0, > sec 7.8.4, and I don't see anything I can match up with these. > > Bjorn Please refer to PCI Express to PCI/PCI-X Bridge Specification, sec 5.2.3.2, 5.2.3.3 and 5.2.3.4. Thanks leoliu-oc
On Fri, Oct 28, 2022 at 07:56:43PM +0800, LeoLiuoc wrote: > 在 2022/10/28 5:56, Bjorn Helgaas 写道: > > On Thu, Oct 27, 2022 at 11:15:54AM +0800, LeoLiu-oc wrote: > > > From: leoliu-oc <leoliu-oc@zhaoxin.com> > > > > > > Define PCI Express Advanced Error Reporting Extended Capabilities bits. > > > > > > Signed-off-by: leoliu-oc <leoliu-oc@zhaoxin.com> > > > --- > > > include/uapi/linux/pci_regs.h | 5 +++++ > > > 1 file changed, 5 insertions(+) > > > > > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > > index 57b8e2ffb1dd..3662106fd8dc 100644 > > > --- a/include/uapi/linux/pci_regs.h > > > +++ b/include/uapi/linux/pci_regs.h > > > @@ -799,6 +799,11 @@ > > > #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ > > > #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ > > > +/* PCI Express Advanced Error Reporting Extended Capabilities for Bridges */ > > > +#define PCI_ERR_UNCOR_MASK2 0x30 /* Secondary Uncorrectable Error Mask */ > > > +#define PCI_ERR_UNCOR_SEVER2 0x34 /* Secondary Uncorrectable Error Severit */ > > > +#define PCI_ERR_CAP2 0x38 /* Secondary Advanced Error Capabilities */ > > > > Can you include a spec reference for these? I'm looking at PCIe r6.0, > > sec 7.8.4, and I don't see anything I can match up with these. > > > Please refer to PCI Express to PCI/PCI-X Bridge Specification, sec 5.2.3.2, > 5.2.3.3 and 5.2.3.4. Thanks, I had forgotten about that spec from 2003 :) I wish they had incorporated the material, or at least a reference to it, into the PCIe base spec like they did with a lot of other similar material. Please include a short comment in the header file, e.g., /* PCIe-to-PCI/PCI-X Bridge Spec r1.0, sec 5.2.3 */
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 57b8e2ffb1dd..3662106fd8dc 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -799,6 +799,11 @@ #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ +/* PCI Express Advanced Error Reporting Extended Capabilities for Bridges */ +#define PCI_ERR_UNCOR_MASK2 0x30 /* Secondary Uncorrectable Error Mask */ +#define PCI_ERR_UNCOR_SEVER2 0x34 /* Secondary Uncorrectable Error Severit */ +#define PCI_ERR_CAP2 0x38 /* Secondary Advanced Error Capabilities */ + /* Virtual Channel */ #define PCI_VC_PORT_CAP1 0x04 #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */