| Message ID | 20220720055436epcms2p63896ebe4e2131e3844044d0112288570@epcms2p6 |
|---|---|
| State | New |
| Headers | show |
| Series | [v4,1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller | expand |
On Wed, 20 Jul 2022 14:54:36 +0900, Wangseok Lee wrote: > Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform > of Axis Communications and PCIe controller is designed based on Design-Ware > PCIe controller. > > Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com> > --- > v3->v4 : > -Add missing properties > > v2->v3 : > -Modify version history to fit the linux commit rule > -Remove 'Device Tree Bindings' on title > -Remove clock-names entries > -Change node name to soc from artpec8 on excamples > > v1->v2 : > -'make dt_binding_check' result improvement > -Add the missing property list > -Align the indentation of continued lines/entries > --- > .../bindings/pci/axis,artpec8-pcie-ep.yaml | 138 +++++++++++++++++++ > .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 148 +++++++++++++++++++++ > 2 files changed, 286 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml > create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.example.dtb: pcie-ep@17200000: Unevaluated properties are not allowed ('#interrupt-cells', 'bus-range', 'interrupt-names', 'samsung,syscon-bus-p-fsys', 'samsung,syscon-bus-s-fsys' were unexpected) From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.example.dtb: pcie@17200000: Unevaluated properties are not allowed ('samsung,syscon-bus-p-fsys', 'samsung,syscon-bus-s-fsys' were unexpected) From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On 20/07/2022 07:54, Wangseok Lee wrote: > Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform > of Axis Communications and PCIe controller is designed based on Design-Ware > PCIe controller. > > Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com> > --- > v3->v4 : > -Add missing properties > > v2->v3 : > -Modify version history to fit the linux commit rule > -Remove 'Device Tree Bindings' on title > -Remove clock-names entries > -Change node name to soc from artpec8 on excamples Please rebase on newest Linux kernel or linux-next and use get_maintainers.pl script. > > v1->v2 : > -'make dt_binding_check' result improvement > -Add the missing property list > -Align the indentation of continued lines/entries > --- > .../bindings/pci/axis,artpec8-pcie-ep.yaml | 138 +++++++++++++++++++ > .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 148 +++++++++++++++++++++ > 2 files changed, 286 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml > create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml > new file mode 100644 > index 0000000..435e86f > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml > @@ -0,0 +1,138 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie-ep.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARTPEC-8 SoC PCIe Controller > + > +maintainers: > + - Jesper Nilsson <jesper.nilsson@axis.com> > + > +description: |+ > + This PCIe end-point controller is based on the Synopsys DesignWare PCIe IP > + and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. > + > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# > + > +properties: > + compatible: > + const: axis,artpec8-pcie-ep > + > + reg: > + items: > + - description: Data Bus Interface (DBI) registers. > + - description: Data Bus Interface (DBI2) registers. > + - description: PCIe address space region. > + > + reg-names: > + items: > + - const: dbi > + - const: dbi2 > + - const: addr_space > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: PIPE clock, used by the controller to clock the PIPE > + - description: PCIe dbi clock, ungated version > + - description: PCIe master clock, ungated version > + - description: PCIe slave clock, ungated version > + > + clock-names: > + items: > + - const: pipe > + - const: dbi > + - const: mstr > + - const: slv > + > + samsung,fsys-sysreg: > + description: > + Phandle to system register of fsys block. > + $ref: /schemas/types.yaml#/definitions/phandle Since you wrote this is one register, I expect offset: https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42 > + > + samsung,syscon-phandle: > + description: > + Phandle to the PMU system controller node. > + $ref: /schemas/types.yaml#/definitions/phandle > + > + samsung,fsys-bus-s: > + description: > + Phandle to bus-s of fsys block, this register > + is additional control sysreg in fsys block and > + this is used for pcie slave control setting. > + $ref: /schemas/types.yaml#/definitions/phandle Ditto > + > + samsung,fsys-bus-p: > + description: > + Phandle to bus-p of fsys block, this register > + is additional control sysreg in fsys block and > + this is used for pcie dbi control setting. > + $ref: /schemas/types.yaml#/definitions/phandle Ditto > + > + phys: > + maxItems: 1 > + > + phy-names: > + items: > + - const: pcie_phy > + > + num-lanes: > + const: 2 > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - interrupt-names > + - clocks > + - clock-names > + - samsung,fsys-sysreg > + - samsung,syscon-phandle > + - samsung,syscon-bus-s-fsys This does not match what you wrote in properties. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml new file mode 100644 index 0000000..435e86f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARTPEC-8 SoC PCIe Controller + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + +description: |+ + This PCIe end-point controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +properties: + compatible: + const: axis,artpec8-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: Data Bus Interface (DBI2) registers. + - description: PCIe address space region. + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: addr_space + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PIPE clock, used by the controller to clock the PIPE + - description: PCIe dbi clock, ungated version + - description: PCIe master clock, ungated version + - description: PCIe slave clock, ungated version + + clock-names: + items: + - const: pipe + - const: dbi + - const: mstr + - const: slv + + samsung,fsys-sysreg: + description: + Phandle to system register of fsys block. + $ref: /schemas/types.yaml#/definitions/phandle + + samsung,syscon-phandle: + description: + Phandle to the PMU system controller node. + $ref: /schemas/types.yaml#/definitions/phandle + + samsung,fsys-bus-s: + description: + Phandle to bus-s of fsys block, this register + is additional control sysreg in fsys block and + this is used for pcie slave control setting. + $ref: /schemas/types.yaml#/definitions/phandle + + samsung,fsys-bus-p: + description: + Phandle to bus-p of fsys block, this register + is additional control sysreg in fsys block and + this is used for pcie dbi control setting. + $ref: /schemas/types.yaml#/definitions/phandle + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie_phy + + num-lanes: + const: 2 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - samsung,fsys-sysreg + - samsung,syscon-phandle + - samsung,syscon-bus-s-fsys + - samsung,syscon-bus-p-fsys + - phys + - phy-names + - num-lanes + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie_ep: pcie-ep@17200000 { + compatible = "axis,artpec8-pcie-ep"; + reg = <0x0 0x17200000 0x0 0x1000>, + <0x0 0x17201000 0x0 0x1000>, + <0x2 0x00000000 0x6 0x00000000>; + reg-names = "dbi", "dbi2", "addr_space"; + #interrupt-cells = <1>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + clocks = <&clock_cmu_fsys 39>, + <&clock_cmu_fsys 38>, + <&clock_cmu_fsys 37>, + <&clock_cmu_fsys 36>; + clock-names = "pipe", "dbi", "mstr", "slv"; + samsung,fsys-sysreg = <&syscon_fsys>; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,syscon-bus-s-fsys = <&syscon_bus_s_fsys>; + samsung,syscon-bus-p-fsys = <&syscon_bus_p_fsys>; + phys = <&pcie_phy>; + phy-names = "pcie_phy"; + num-lanes = <2>; + bus-range = <0x00 0xff>; + num-ib-windows = <16>; + num-ob-windows = <16>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml new file mode 100644 index 0000000..b7cff4f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Artpec-8 SoC PCIe Controller + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + +description: |+ + This PCIe host controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: axis,artpec8-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: External Local Bus interface (ELBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: elbi + - const: config + + ranges: + maxItems: 2 + + num-lanes: + const: 2 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PIPE clock, used by the controller to clock the PIPE + - description: PCIe dbi clock, ungated version + - description: PCIe master clock, ungated version + - description: PCIe slave clock, ungated version + + clock-names: + items: + - const: pipe + - const: dbi + - const: mstr + - const: slv + + samsung,fsys-sysreg: + description: + Phandle to system register of fsys block. + $ref: /schemas/types.yaml#/definitions/phandle + + samsung,syscon-phandle: + description: + Phandle to the PMU system controller node. + $ref: /schemas/types.yaml#/definitions/phandle + + samsung,fsys-bus-s: + description: + Phandle to bus-s of fsys block, this register + is additional control sysreg in fsys block and + this is used for pcie slave control setting. + $ref: /schemas/types.yaml#/definitions/phandle + + samsung,fsys-bus-p: + description: + Phandle to bus-p of fsys block, this register + is additional control sysreg in fsys block and + this is used for pcie dbi control setting. + $ref: /schemas/types.yaml#/definitions/phandle + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie_phy + +required: + - compatible + - reg + - reg-names + - device_type + - ranges + - num-lanes + - interrupts + - interrupt-names + - clocks + - clock-names + - samsung,fsys-sysreg + - samsung,syscon-phandle + - samsung,syscon-bus-s-fsys + - samsung,syscon-bus-p-fsys + - phys + - phy-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie: pcie@17200000 { + compatible = "axis,artpec8-pcie"; + reg = <0x0 0x17200000 0x0 0x1000>, + <0x0 0x16ca0000 0x0 0x2000>, + <0x7 0x0001e000 0x0 0x2000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = </* non-prefetchable memory */ + 0x83000000 0x0 0x0000000 0x2 0x00000000 0x5 0x00000000 + /* downstream I/O */ + 0x81000000 0x0 0x0000000 0x7 0x00000000 0x0 0x00010000>; + num-lanes = <2>; + bus-range = <0x00 0xff>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "intr"; + #interrupt-cells = <1>; + clocks = <&cmu_fsys 39>, + <&cmu_fsys 38>, + <&cmu_fsys 37>, + <&cmu_fsys 36>; + clock-names = "pipe", "dbi", "mstr", "slv"; + samsung,fsys-sysreg = <&syscon_fsys>; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,syscon-bus-s-fsys = <&syscon_bus_s_fsys>; + samsung,syscon-bus-p-fsys = <&syscon_bus_p_fsys>; + phys = <&pcie_phy>; + phy-names = "pcie_phy"; + }; + }; +...
Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform of Axis Communications and PCIe controller is designed based on Design-Ware PCIe controller. Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com> --- v3->v4 : -Add missing properties v2->v3 : -Modify version history to fit the linux commit rule -Remove 'Device Tree Bindings' on title -Remove clock-names entries -Change node name to soc from artpec8 on excamples v1->v2 : -'make dt_binding_check' result improvement -Add the missing property list -Align the indentation of continued lines/entries --- .../bindings/pci/axis,artpec8-pcie-ep.yaml | 138 +++++++++++++++++++ .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 148 +++++++++++++++++++++ 2 files changed, 286 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml