| Message ID | 20220624041950.559155-7-dan.j.williams@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | CXL PMEM Region Provisioning | expand |
On Thu, 23 Jun 2022 21:19:36 -0700 Dan Williams <dan.j.williams@intel.com> wrote: > The port scanning algorithm in devm_cxl_enumerate_ports() walks up the > topology and adds cxl_port objects starting from the root down to the > endpoint. When those ports are initially created they know all their > dports, but they do not know the downstream cxl_port instance that > represents the next descendant in the topology. Rework create_endpoint() > into devm_cxl_add_endpoint() that enumerates the downstream cxl_port > topology into each port's 'struct cxl_ep' record for each endpoint it > that the port is an ancestor. > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> I'm doing my normal moaning about tidying up in a patch that makes a more serious change. Ideally pull that out, but meh if it's a real pain I can live with it as long as you call it out in the patch description. With that Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/core/port.c | 41 +++++++++++++++++++++++++++++++++++++++++ > drivers/cxl/cxl.h | 7 ++++++- > drivers/cxl/mem.c | 30 +----------------------------- > 3 files changed, 48 insertions(+), 30 deletions(-) > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 08a380d20cf1..2e56903399c2 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -1089,6 +1089,47 @@ static struct cxl_ep *cxl_ep_load(struct cxl_port *port, > return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); > } > > +int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd, > + struct cxl_dport *parent_dport) > +{ > + struct cxl_port *parent_port = parent_dport->port; > + struct cxl_dev_state *cxlds = cxlmd->cxlds; > + struct cxl_port *endpoint, *iter, *down; > + int rc; > + > + /* > + * Now that the path to the root is established record all the > + * intervening ports in the chain. > + */ > + for (iter = parent_port, down = NULL; !is_cxl_root(iter); > + down = iter, iter = to_cxl_port(iter->dev.parent)) { > + struct cxl_ep *ep; > + > + ep = cxl_ep_load(iter, cxlmd); > + ep->next = down; > + } > + > + endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev, > + cxlds->component_reg_phys, parent_dport); > + if (IS_ERR(endpoint)) > + return PTR_ERR(endpoint); > + > + dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev)); > + > + rc = cxl_endpoint_autoremove(cxlmd, endpoint); > + if (rc) > + return rc; > + > + if (!endpoint->dev.driver) { > + dev_err(&cxlmd->dev, "%s failed probe\n", > + dev_name(&endpoint->dev)); > + return -ENXIO; > + } > + > + return 0; > +} > +EXPORT_SYMBOL_NS_GPL(devm_cxl_add_endpoint, CXL); > + > static void cxl_detach_ep(void *data) > { > struct cxl_memdev *cxlmd = data; > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index 0211cf0d3574..f761cf78cc05 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -371,11 +371,14 @@ struct cxl_dport { > /** > * struct cxl_ep - track an endpoint's interest in a port > * @ep: device that hosts a generic CXL endpoint (expander or accelerator) > - * @dport: which dport routes to this endpoint on this port > + * @dport: which dport routes to this endpoint on @port fix is good, but shouldn't be in this patch really.. > + * @next: cxl switch port across the link attached to @dport NULL if > + * attached to an endpoint > */ > struct cxl_ep { > struct device *ep; > struct cxl_dport *dport; > + struct cxl_port *next; > }; > > /* > @@ -398,6 +401,8 @@ struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); > struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, > resource_size_t component_reg_phys, > struct cxl_dport *parent_dport); > +int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd, > + struct cxl_dport *parent_dport); > struct cxl_port *find_cxl_root(struct device *dev); > int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); > int cxl_bus_rescan(void); > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 2786d3402c9e..64ccf053d32c 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -25,34 +25,6 @@ > * in higher level operations. > */ > > -static int create_endpoint(struct cxl_memdev *cxlmd, > - struct cxl_dport *parent_dport) > -{ > - struct cxl_port *parent_port = parent_dport->port; > - struct cxl_dev_state *cxlds = cxlmd->cxlds; > - struct cxl_port *endpoint; > - int rc; > - > - endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev, > - cxlds->component_reg_phys, parent_dport); > - if (IS_ERR(endpoint)) > - return PTR_ERR(endpoint); > - > - dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev)); > - > - rc = cxl_endpoint_autoremove(cxlmd, endpoint); > - if (rc) > - return rc; > - > - if (!endpoint->dev.driver) { > - dev_err(&cxlmd->dev, "%s failed probe\n", > - dev_name(&endpoint->dev)); > - return -ENXIO; > - } > - > - return 0; > -} > - > static void enable_suspend(void *data) > { > cxl_mem_active_dec(); > @@ -116,7 +88,7 @@ static int cxl_mem_probe(struct device *dev) > goto unlock; > } > > - rc = create_endpoint(cxlmd, dport); > + rc = devm_cxl_add_endpoint(cxlmd, dport); > unlock: > device_unlock(&parent_port->dev); > put_device(&parent_port->dev);
Jonathan Cameron wrote: > On Thu, 23 Jun 2022 21:19:36 -0700 > Dan Williams <dan.j.williams@intel.com> wrote: > > > The port scanning algorithm in devm_cxl_enumerate_ports() walks up the > > topology and adds cxl_port objects starting from the root down to the > > endpoint. When those ports are initially created they know all their > > dports, but they do not know the downstream cxl_port instance that > > represents the next descendant in the topology. Rework create_endpoint() > > into devm_cxl_add_endpoint() that enumerates the downstream cxl_port > > topology into each port's 'struct cxl_ep' record for each endpoint it > > that the port is an ancestor. > > > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > > I'm doing my normal moaning about tidying up in a patch that makes > a more serious change. Ideally pull that out, but meh if it's a real pain > I can live with it as long as you call it out in the patch description. No worries, I would expect to be able to ask others to do the same and I should be more careful to collect these unrelated fixups separately. > > With that > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > > --- > > drivers/cxl/core/port.c | 41 +++++++++++++++++++++++++++++++++++++++++ > > drivers/cxl/cxl.h | 7 ++++++- > > drivers/cxl/mem.c | 30 +----------------------------- > > 3 files changed, 48 insertions(+), 30 deletions(-) > > > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > > index 08a380d20cf1..2e56903399c2 100644 > > --- a/drivers/cxl/core/port.c > > +++ b/drivers/cxl/core/port.c > > @@ -1089,6 +1089,47 @@ static struct cxl_ep *cxl_ep_load(struct cxl_port *port, > > return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); > > } > > > > +int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd, > > + struct cxl_dport *parent_dport) > > +{ > > + struct cxl_port *parent_port = parent_dport->port; > > + struct cxl_dev_state *cxlds = cxlmd->cxlds; > > + struct cxl_port *endpoint, *iter, *down; > > + int rc; > > + > > + /* > > + * Now that the path to the root is established record all the > > + * intervening ports in the chain. > > + */ > > + for (iter = parent_port, down = NULL; !is_cxl_root(iter); > > + down = iter, iter = to_cxl_port(iter->dev.parent)) { > > + struct cxl_ep *ep; > > + > > + ep = cxl_ep_load(iter, cxlmd); > > + ep->next = down; > > + } > > + > > + endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev, > > + cxlds->component_reg_phys, parent_dport); > > + if (IS_ERR(endpoint)) > > + return PTR_ERR(endpoint); > > + > > + dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev)); > > + > > + rc = cxl_endpoint_autoremove(cxlmd, endpoint); > > + if (rc) > > + return rc; > > + > > + if (!endpoint->dev.driver) { > > + dev_err(&cxlmd->dev, "%s failed probe\n", > > + dev_name(&endpoint->dev)); > > + return -ENXIO; > > + } > > + > > + return 0; > > +} > > +EXPORT_SYMBOL_NS_GPL(devm_cxl_add_endpoint, CXL); > > + > > static void cxl_detach_ep(void *data) > > { > > struct cxl_memdev *cxlmd = data; > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > > index 0211cf0d3574..f761cf78cc05 100644 > > --- a/drivers/cxl/cxl.h > > +++ b/drivers/cxl/cxl.h > > @@ -371,11 +371,14 @@ struct cxl_dport { > > /** > > * struct cxl_ep - track an endpoint's interest in a port > > * @ep: device that hosts a generic CXL endpoint (expander or accelerator) > > - * @dport: which dport routes to this endpoint on this port > > + * @dport: which dport routes to this endpoint on @port > > fix is good, but shouldn't be in this patch really.. Rolled this into "[PATCH 25/46] cxl/port: Record dport in endpoint references" where @dport was introduced.
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 08a380d20cf1..2e56903399c2 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1089,6 +1089,47 @@ static struct cxl_ep *cxl_ep_load(struct cxl_port *port, return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev); } +int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd, + struct cxl_dport *parent_dport) +{ + struct cxl_port *parent_port = parent_dport->port; + struct cxl_dev_state *cxlds = cxlmd->cxlds; + struct cxl_port *endpoint, *iter, *down; + int rc; + + /* + * Now that the path to the root is established record all the + * intervening ports in the chain. + */ + for (iter = parent_port, down = NULL; !is_cxl_root(iter); + down = iter, iter = to_cxl_port(iter->dev.parent)) { + struct cxl_ep *ep; + + ep = cxl_ep_load(iter, cxlmd); + ep->next = down; + } + + endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev, + cxlds->component_reg_phys, parent_dport); + if (IS_ERR(endpoint)) + return PTR_ERR(endpoint); + + dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev)); + + rc = cxl_endpoint_autoremove(cxlmd, endpoint); + if (rc) + return rc; + + if (!endpoint->dev.driver) { + dev_err(&cxlmd->dev, "%s failed probe\n", + dev_name(&endpoint->dev)); + return -ENXIO; + } + + return 0; +} +EXPORT_SYMBOL_NS_GPL(devm_cxl_add_endpoint, CXL); + static void cxl_detach_ep(void *data) { struct cxl_memdev *cxlmd = data; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 0211cf0d3574..f761cf78cc05 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -371,11 +371,14 @@ struct cxl_dport { /** * struct cxl_ep - track an endpoint's interest in a port * @ep: device that hosts a generic CXL endpoint (expander or accelerator) - * @dport: which dport routes to this endpoint on this port + * @dport: which dport routes to this endpoint on @port + * @next: cxl switch port across the link attached to @dport NULL if + * attached to an endpoint */ struct cxl_ep { struct device *ep; struct cxl_dport *dport; + struct cxl_port *next; }; /* @@ -398,6 +401,8 @@ struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, resource_size_t component_reg_phys, struct cxl_dport *parent_dport); +int devm_cxl_add_endpoint(struct cxl_memdev *cxlmd, + struct cxl_dport *parent_dport); struct cxl_port *find_cxl_root(struct device *dev); int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); int cxl_bus_rescan(void); diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 2786d3402c9e..64ccf053d32c 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -25,34 +25,6 @@ * in higher level operations. */ -static int create_endpoint(struct cxl_memdev *cxlmd, - struct cxl_dport *parent_dport) -{ - struct cxl_port *parent_port = parent_dport->port; - struct cxl_dev_state *cxlds = cxlmd->cxlds; - struct cxl_port *endpoint; - int rc; - - endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev, - cxlds->component_reg_phys, parent_dport); - if (IS_ERR(endpoint)) - return PTR_ERR(endpoint); - - dev_dbg(&cxlmd->dev, "add: %s\n", dev_name(&endpoint->dev)); - - rc = cxl_endpoint_autoremove(cxlmd, endpoint); - if (rc) - return rc; - - if (!endpoint->dev.driver) { - dev_err(&cxlmd->dev, "%s failed probe\n", - dev_name(&endpoint->dev)); - return -ENXIO; - } - - return 0; -} - static void enable_suspend(void *data) { cxl_mem_active_dec(); @@ -116,7 +88,7 @@ static int cxl_mem_probe(struct device *dev) goto unlock; } - rc = create_endpoint(cxlmd, dport); + rc = devm_cxl_add_endpoint(cxlmd, dport); unlock: device_unlock(&parent_port->dev); put_device(&parent_port->dev);
The port scanning algorithm in devm_cxl_enumerate_ports() walks up the topology and adds cxl_port objects starting from the root down to the endpoint. When those ports are initially created they know all their dports, but they do not know the downstream cxl_port instance that represents the next descendant in the topology. Rework create_endpoint() into devm_cxl_add_endpoint() that enumerates the downstream cxl_port topology into each port's 'struct cxl_ep' record for each endpoint it that the port is an ancestor. Signed-off-by: Dan Williams <dan.j.williams@intel.com> --- drivers/cxl/core/port.c | 41 +++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 7 ++++++- drivers/cxl/mem.c | 30 +----------------------------- 3 files changed, 48 insertions(+), 30 deletions(-)