diff mbox series

[39/46] cxl/acpi: Add a host-bridge index lookup mechanism

Message ID 20220624041950.559155-14-dan.j.williams@intel.com
State New
Headers show
Series CXL PMEM Region Provisioning | expand

Commit Message

Dan Williams June 24, 2022, 4:19 a.m. UTC
The ACPI CXL Fixed Memory Window Structure (CFMWS) defines multiple
methods to determine which host bridge provides access to a given
endpoint relative to that device's position in the interleave. The
"Interleave Arithmetic" defines either a "standard modulo" /
round-random algorithm, or "xormap" based algorithm which can be defined
as a non-linear transform. Given that there are already more options
beyond "standard modulo" and that "xormap" may turn out to be ACPI CXL
specific, provide a callback for the region provisioning code to map
endpoint positions back to expected host bridge id (cxl_dport target).

For now just support the simple modulo math case and save the xormap for
a follow-on change.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 drivers/cxl/core/port.c | 15 +++++++++++++++
 drivers/cxl/cxl.h       |  2 ++
 2 files changed, 17 insertions(+)

Comments

Jonathan Cameron June 30, 2022, 3:48 p.m. UTC | #1
On Thu, 23 Jun 2022 21:19:43 -0700
Dan Williams <dan.j.williams@intel.com> wrote:

> The ACPI CXL Fixed Memory Window Structure (CFMWS) defines multiple
> methods to determine which host bridge provides access to a given
> endpoint relative to that device's position in the interleave. The
> "Interleave Arithmetic" defines either a "standard modulo" /
> round-random algorithm, or "xormap" based algorithm which can be defined
> as a non-linear transform. Given that there are already more options
> beyond "standard modulo" and that "xormap" may turn out to be ACPI CXL
> specific, provide a callback for the region provisioning code to map
> endpoint positions back to expected host bridge id (cxl_dport target).
> 
> For now just support the simple modulo math case and save the xormap for
> a follow-on change.
> 
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  drivers/cxl/core/port.c | 15 +++++++++++++++
>  drivers/cxl/cxl.h       |  2 ++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 562a6453249b..7756409d0a58 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1422,6 +1422,20 @@ static int decoder_populate_targets(struct cxl_switch_decoder *cxlsd,
>  	return rc;
>  }
>  
> +static struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos)
> +{
> +	struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
> +	struct cxl_decoder *cxld = &cxlsd->cxld;
> +	int iw;
> +
> +	iw = cxld->interleave_ways;
> +	if (dev_WARN_ONCE(&cxld->dev, iw != cxlsd->nr_targets,
> +			  "misconfigured root decoder\n"))
> +		return NULL;
> +
> +	return cxlrd->cxlsd.target[pos % iw];
> +}
> +
>  static struct lock_class_key cxl_decoder_key;
>  
>  /**
> @@ -1466,6 +1480,7 @@ static struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port,
>  				if (rc < 0)
>  					goto err;
>  				atomic_set(&cxlrd->region_id, rc);
> +				cxlrd->calc_hb = cxl_hb_modulo;
>  			} else
>  				cxlsd = NULL;
>  		} else {
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 9340deccad4f..30227348f768 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -315,11 +315,13 @@ struct cxl_switch_decoder {
>   * struct cxl_root_decoder - Static platform CXL address decoder
>   * @res: host / parent resource for region allocations
>   * @region_id: region id for next region provisioning event
> + * @calc_hb: which host bridge covers the n'th position by granularity
>   * @cxlsd: base cxl switch decoder
>   */
>  struct cxl_root_decoder {
>  	struct resource *res;
>  	atomic_t region_id;
> +	struct cxl_dport *(*calc_hb)(struct cxl_root_decoder *cxlrd, int pos);
>  	struct cxl_switch_decoder cxlsd;
>  };
>
diff mbox series

Patch

diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 562a6453249b..7756409d0a58 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1422,6 +1422,20 @@  static int decoder_populate_targets(struct cxl_switch_decoder *cxlsd,
 	return rc;
 }
 
+static struct cxl_dport *cxl_hb_modulo(struct cxl_root_decoder *cxlrd, int pos)
+{
+	struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
+	struct cxl_decoder *cxld = &cxlsd->cxld;
+	int iw;
+
+	iw = cxld->interleave_ways;
+	if (dev_WARN_ONCE(&cxld->dev, iw != cxlsd->nr_targets,
+			  "misconfigured root decoder\n"))
+		return NULL;
+
+	return cxlrd->cxlsd.target[pos % iw];
+}
+
 static struct lock_class_key cxl_decoder_key;
 
 /**
@@ -1466,6 +1480,7 @@  static struct cxl_decoder *cxl_decoder_alloc(struct cxl_port *port,
 				if (rc < 0)
 					goto err;
 				atomic_set(&cxlrd->region_id, rc);
+				cxlrd->calc_hb = cxl_hb_modulo;
 			} else
 				cxlsd = NULL;
 		} else {
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 9340deccad4f..30227348f768 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -315,11 +315,13 @@  struct cxl_switch_decoder {
  * struct cxl_root_decoder - Static platform CXL address decoder
  * @res: host / parent resource for region allocations
  * @region_id: region id for next region provisioning event
+ * @calc_hb: which host bridge covers the n'th position by granularity
  * @cxlsd: base cxl switch decoder
  */
 struct cxl_root_decoder {
 	struct resource *res;
 	atomic_t region_id;
+	struct cxl_dport *(*calc_hb)(struct cxl_root_decoder *cxlrd, int pos);
 	struct cxl_switch_decoder cxlsd;
 };