| Message ID | 20211120000250.1663391-8-ben.widawsky@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add drivers for CXL ports and mem devices | expand |
On Fri, 19 Nov 2021 16:02:34 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > While the new definitions are yet necessary at this point, they are > introduced at this point to help solidify the newly minted schema for > naming registers. > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huwei.com> > > --- > This was split from > https://lore.kernel.org/linux-cxl/20211103170552.55ae5u7uvurkync6@intel.com/T/#u > per Dan's request. > --- > drivers/cxl/pci.h | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h > index 29b8eaef3a0a..8ae2b4adc59d 100644 > --- a/drivers/cxl/pci.h > +++ b/drivers/cxl/pci.h > @@ -16,6 +16,21 @@ > /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ > #define CXL_DVSEC_PCIE_DEVICE 0 > > +/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */ > +#define CXL_DVSEC_FUNCTION_MAP 2 > + > +/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */ > +#define CXL_DVSEC_PORT_EXTENSIONS 3 > + > +/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */ > +#define CXL_DVSEC_PORT_GPF 4 > + > +/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */ > +#define CXL_DVSEC_DEVICE_GPF 5 > + > +/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */ > +#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7 > + > /* CXL 2.0 8.1.9: Register Locator DVSEC */ > #define CXL_DVSEC_REG_LOCATOR 8 > #define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC
On 21-11-22 15:22:24, Jonathan Cameron wrote: > On Fri, 19 Nov 2021 16:02:34 -0800 > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > While the new definitions are yet necessary at this point, they are > > introduced at this point to help solidify the newly minted schema for > > naming registers. > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huwei.com> Thanks. I realized on re-reading this I didn't like the commit message. I reworded to this: While the new definitions are not yet necessary at this point, they are introduced to help solidify the newly minted schema for naming registers. Please let me know if you'd like me to drop your reviewed-by tag. > > > > > --- > > This was split from > > https://lore.kernel.org/linux-cxl/20211103170552.55ae5u7uvurkync6@intel.com/T/#u > > per Dan's request. > > --- > > drivers/cxl/pci.h | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h > > index 29b8eaef3a0a..8ae2b4adc59d 100644 > > --- a/drivers/cxl/pci.h > > +++ b/drivers/cxl/pci.h > > @@ -16,6 +16,21 @@ > > /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ > > #define CXL_DVSEC_PCIE_DEVICE 0 > > > > +/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */ > > +#define CXL_DVSEC_FUNCTION_MAP 2 > > + > > +/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */ > > +#define CXL_DVSEC_PORT_EXTENSIONS 3 > > + > > +/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */ > > +#define CXL_DVSEC_PORT_GPF 4 > > + > > +/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */ > > +#define CXL_DVSEC_DEVICE_GPF 5 > > + > > +/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */ > > +#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7 > > + > > /* CXL 2.0 8.1.9: Register Locator DVSEC */ > > #define CXL_DVSEC_REG_LOCATOR 8 > > #define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC >
On Mon, Nov 22, 2021 at 9:32 AM Ben Widawsky <ben.widawsky@intel.com> wrote: > > On 21-11-22 15:22:24, Jonathan Cameron wrote: > > On Fri, 19 Nov 2021 16:02:34 -0800 > > Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > > While the new definitions are yet necessary at this point, they are > > > introduced at this point to help solidify the newly minted schema for > > > naming registers. > > > > > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > > > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huwei.com> > > Thanks. I realized on re-reading this I didn't like the commit message. I > reworded to this: > > While the new definitions are not yet necessary at this point, they are > introduced to help solidify the newly minted schema for naming > registers. > > Please let me know if you'd like me to drop your reviewed-by tag. The typical changelog template for patches like this is: "In preparation for adding features X, Y, and Z, add definitions for A, B, and C." Otherwise, patch looks good. Reviewed-by: Dan Williams <dan.j.williams@intel.com>
diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h index 29b8eaef3a0a..8ae2b4adc59d 100644 --- a/drivers/cxl/pci.h +++ b/drivers/cxl/pci.h @@ -16,6 +16,21 @@ /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ #define CXL_DVSEC_PCIE_DEVICE 0 +/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */ +#define CXL_DVSEC_FUNCTION_MAP 2 + +/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */ +#define CXL_DVSEC_PORT_EXTENSIONS 3 + +/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */ +#define CXL_DVSEC_PORT_GPF 4 + +/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */ +#define CXL_DVSEC_DEVICE_GPF 5 + +/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */ +#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7 + /* CXL 2.0 8.1.9: Register Locator DVSEC */ #define CXL_DVSEC_REG_LOCATOR 8 #define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC
While the new definitions are yet necessary at this point, they are introduced at this point to help solidify the newly minted schema for naming registers. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- This was split from https://lore.kernel.org/linux-cxl/20211103170552.55ae5u7uvurkync6@intel.com/T/#u per Dan's request. --- drivers/cxl/pci.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+)