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[RFC,2/3] dt-bindings: PCI: rockchip: document bus-scan-delay-ms workaround property

Message ID 20201231125214.25733-3-nuumiofi@gmail.com
State New
Headers show
Series provide workaround for Rockchip PCIe bus scan crash with optional delay | expand

Commit Message

Jari Hämäläinen Dec. 31, 2020, 12:52 p.m. UTC
New "rockchip,bus-scan-delay-ms" property can be used to set a delay
before PCIe bus scan as a workaround for some problematic devices causing
a crash in bus scan.

Signed-off-by: Jari Hämäläinen <nuumiofi@gmail.com>
 Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt | 3 +++
 1 file changed, 3 insertions(+)
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diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt
index af34c65773fd..394bdf562d58 100644
--- a/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt
+++ b/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt
@@ -57,6 +57,8 @@  Optional Property:
 	using 24MHz OSC for RC's PHY.
 - ep-gpios: contain the entry for pre-reset GPIO
 - num-lanes: number of lanes to use
+- rockchip,bus-scan-delay-ms: delay before PCIe bus scan in milliseconds.
+	Provides a workaround for some devices causing a crash in bus scan.
 - vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
 - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
 - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
@@ -106,6 +108,7 @@  pcie0: pcie@f8000000 {
 		 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
 	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 		      "pm", "pclk", "aclk";
+	rockchip,bus-scan-delay-ms = <1100>;
 	/* deprecated legacy PHY model */
 	phys = <&pcie_phy>;
 	phy-names = "pcie-phy";