From patchwork Wed Aug 12 16:46:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kelley, Sean V" X-Patchwork-Id: 1343795 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BRbHW2pSqz9sPB for ; Thu, 13 Aug 2020 02:48:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726941AbgHLQsD (ORCPT ); Wed, 12 Aug 2020 12:48:03 -0400 Received: from mga12.intel.com ([192.55.52.136]:33828 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726515AbgHLQrJ (ORCPT ); Wed, 12 Aug 2020 12:47:09 -0400 IronPort-SDR: PLd8YpKRkvi4LRRkeQHXkGyvYpFvwXULLjj72yUpfDEDghQLH0Pmc6zrr1Jt/OZ5SC4qN8bzvA 8wj8F4NNM2bQ== X-IronPort-AV: E=McAfee;i="6000,8403,9711"; a="133538407" X-IronPort-AV: E=Sophos;i="5.76,305,1592895600"; d="scan'208";a="133538407" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2020 09:47:08 -0700 IronPort-SDR: VJy/qUjKBiSitXn1k39kLkfO8iLO7E3q/Msk0m572NgQrTH+aIvVwpYmucDHcCrKM8l9ES3GoU CLAcB0gJQmjQ== X-IronPort-AV: E=Sophos;i="5.76,305,1592895600"; d="scan'208";a="439442616" Received: from ticede-or-099.amr.corp.intel.com (HELO arch-ashland-svkelley.intel.com) ([10.254.58.97]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2020 09:47:07 -0700 From: Sean V Kelley To: bhelgaas@google.com, Jonathan.Cameron@huawei.com, rjw@rjwysocki.net, ashok.raj@intel.com, tony.luck@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, qiuxu.zhuo@intel.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Sean V Kelley Subject: [PATCH v3 02/10] PCI/RCEC: Bind RCEC devices to the Root Port driver Date: Wed, 12 Aug 2020 09:46:51 -0700 Message-Id: <20200812164659.1118946-3-sean.v.kelley@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200812164659.1118946-1-sean.v.kelley@intel.com> References: <20200812164659.1118946-1-sean.v.kelley@intel.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Qiuxu Zhuo If a Root Complex Integrated Endpoint (RCiEP) is implemented, errors may optionally be sent to a corresponding Root Complex Event Collector (RCEC). Each RCiEP must be associated with no more than one RCEC. Interface errors are reported to the OS by RCECs. For an RCEC (technically not a Bridge), error messages "received" from associated RCiEPs must be enabled for "transmission" in order to cause a System Error via the Root Control register or (when the Advanced Error Reporting Capability is present) reporting via the Root Error Command register and logging in the Root Error Status register and Error Source Identification register. Given the commonality with Root Ports and the need to also support AER and PME services for RCECs, extend the Root Port driver to support RCEC devices through the addition of the RCEC Class ID to the driver structure. Co-developed-by: Sean V Kelley Signed-off-by: Sean V Kelley Signed-off-by: Qiuxu Zhuo Reviewed-by: Jonathan Cameron --- drivers/pci/pcie/portdrv_core.c | 8 ++++---- drivers/pci/pcie/portdrv_pci.c | 5 ++++- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c index 50a9522ab07d..99769c636775 100644 --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c @@ -234,11 +234,11 @@ static int get_port_device_capability(struct pci_dev *dev) #endif /* - * Root ports are capable of generating PME too. Root Complex - * Event Collectors can also generate PMEs, but we don't handle - * those yet. + * Root ports and Root Complex Event Collectors are capable + * of generating PME. */ - if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT && + if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || + pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC) && (pcie_ports_native || host->native_pme)) { services |= PCIE_PORT_SERVICE_PME; diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c index 3acf151ae015..d5b109499b10 100644 --- a/drivers/pci/pcie/portdrv_pci.c +++ b/drivers/pci/pcie/portdrv_pci.c @@ -106,7 +106,8 @@ static int pcie_portdrv_probe(struct pci_dev *dev, if (!pci_is_pcie(dev) || ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) && - (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) + (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM) && + (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_EC))) return -ENODEV; status = pcie_port_device_register(dev); @@ -195,6 +196,8 @@ static const struct pci_device_id port_pci_ids[] = { { PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0) }, /* subtractive decode PCI-to-PCI bridge, class type is 060401h */ { PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x01), ~0) }, + /* handle any Root Complex Event Collector */ + { PCI_DEVICE_CLASS(((PCI_CLASS_SYSTEM_RCEC << 8) | 0x00), ~0) }, { }, };