From patchwork Thu May 21 22:40:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 1295742 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=default header.b=VmO8whyZ; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49Sl2X2K5Vz9sPK for ; Fri, 22 May 2020 08:40:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730371AbgEUWkv (ORCPT ); Thu, 21 May 2020 18:40:51 -0400 Received: from mail.kernel.org ([198.145.29.99]:43376 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730329AbgEUWkv (ORCPT ); Thu, 21 May 2020 18:40:51 -0400 Received: from localhost (mobile-166-175-190-200.mycingular.net [166.175.190.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 456CC20756; Thu, 21 May 2020 22:40:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1590100846; bh=LCulSmVvEGpedCU5A/oowhvk6TKbx0Rgu/OGGvqwp2s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VmO8whyZYns9482ZhPiLCd1hWspWkll+iRfks+Hdd0qs4JAcfo1IHlIebdOAfBs4T 8lOikyKQGB1SPvowYs35K/neiMVMW0Uf4KxlhxnGMfiCJ1AJLDxnngTkpHCOoW7mST 3+5aZtPXBs5PFhtAXVVIe79evHMl+iu6LVCj/ikc= From: Bjorn Helgaas To: Martin Mares Cc: Mika Westerberg , Kai-Heng Feng , Myron Stowe , linux-pci@vger.kernel.org, Bjorn Helgaas Subject: [PATCH 1/2] lspci: Decode PCIe Link Capabilities 2, expand Link Status 2 Date: Thu, 21 May 2020 17:40:29 -0500 Message-Id: <20200521224030.1193617-2-helgaas@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200521224030.1193617-1-helgaas@kernel.org> References: <20200521224030.1193617-1-helgaas@kernel.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Bjorn Helgaas Decode Link Capabilities 2, which includes the Supported Link Speeds Vector, and decode more fields of Link Status 2. The test case (data from https://bugzilla.kernel.org/show_bug.cgi?id=206837 comment #21) includes a Thunderbolt Downstream Port that advertises 2.5-8GT/s support in Link Capabilities 2. Signed-off-by: Bjorn Helgaas --- lib/header.h | 10 + ls-caps.c | 93 ++- tests/cap-exp-lnkcap2 | 1317 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1418 insertions(+), 2 deletions(-) create mode 100644 tests/cap-exp-lnkcap2 diff --git a/lib/header.h b/lib/header.h index bfdcc80..93a6e4f 100644 --- a/lib/header.h +++ b/lib/header.h @@ -901,6 +901,11 @@ #define PCI_EXP_DEV2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */ #define PCI_EXP_DEVSTA2 0x2a /* Device Status */ #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */ +#define PCI_EXP_LNKCAP2_SPEED(x) (((x) >> 1) & 0x7f) +#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink Supported */ +#define PCI_EXP_LNKCAP2_RETIMER 0x00800000 /* Retimer Supported */ +#define PCI_EXP_LNKCAP2_2RETIMERS 0x01000000 /* 2 Retimers Supported */ +#define PCI_EXP_LNKCAP2_DRS 0x80000000 /* Device Readiness Status */ #define PCI_EXP_LNKCTL2 0x30 /* Link Control */ #define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */ #define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */ @@ -917,6 +922,11 @@ #define PCI_EXP_LINKSTA2_EQU_PHASE2 0x08 /* Equalization Phase 2 Successful */ #define PCI_EXP_LINKSTA2_EQU_PHASE3 0x10 /* Equalization Phase 3 Successful */ #define PCI_EXP_LINKSTA2_EQU_REQ 0x20 /* Link Equalization Request */ +#define PCI_EXP_LINKSTA2_RETIMER 0x0040 /* Retimer Detected */ +#define PCI_EXP_LINKSTA2_2RETIMERS 0x0080 /* 2 Retimers Detected */ +#define PCI_EXP_LINKSTA2_CROSSLINK(x) (((x) >> 8) & 0x3) /* Crosslink Res */ +#define PCI_EXP_LINKSTA2_COMPONENT(x) (((x) >> 12) & 0x7) /* Presence */ +#define PCI_EXP_LINKSTA2_DRS_RCVD 0x8000 /* DRS Msg Received */ #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */ #define PCI_EXP_SLTCTL2 0x38 /* Slot Control */ #define PCI_EXP_SLTSTA2 0x3a /* Slot Status */ diff --git a/ls-caps.c b/ls-caps.c index a6705eb..c8a8bd6 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -649,6 +649,13 @@ cap_msi(struct device *d, int where, int cap) } } +static int exp_downstream_port(int type) +{ + return type == PCI_EXP_TYPE_ROOT_PORT || + type == PCI_EXP_TYPE_DOWNSTREAM || + type == PCI_EXP_TYPE_PCIE_BRIDGE; /* PCI/PCI-X to PCIe Bridge */ +} + static float power_limit(int value, int scale) { static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 }; @@ -1151,6 +1158,29 @@ static void cap_express_dev2(struct device *d, int where, int type) } } +static const char *cap_express_link2_speed_cap(int vector) +{ + /* + * Per PCIe r5.0, sec 8.2.1, a device must support 2.5GT/s and is not + * permitted to skip support for any data rates between 2.5GT/s and the + * highest supported rate. + */ + if (vector & 0x60) + return "RsvdP"; + if (vector & 0x10) + return "2.5-32GT/s"; + if (vector & 0x08) + return "2.5-16GT/s"; + if (vector & 0x04) + return "2.5-8GT/s"; + if (vector & 0x02) + return "2.5-5GT/s"; + if (vector & 0x01) + return "2.5GT/s"; + + return "Unknown"; +} + static const char *cap_express_link2_speed(int type) { switch (type) @@ -1202,12 +1232,59 @@ static const char *cap_express_link2_transmargin(int type) } } +static const char *cap_express_link2_crosslink_res(int crosslink) +{ + switch (crosslink) + { + case 0: + return "unsupported"; + case 1: + return "Upstream Port"; + case 2: + return "Downstream Port"; + default: + return "incomplete"; + } +} + +static const char *cap_express_link2_component(int presence) +{ + switch (presence) + { + case 0: + return "Link Down - Not Determined"; + case 1: + return "Link Down - Not Present"; + case 2: + return "Link Down - Present"; + case 4: + return "Link Up - Present"; + case 5: + return "Link Up - Present and DRS Received"; + default: + return "Reserved"; + } +} + static void cap_express_link2(struct device *d, int where, int type) { + u32 l = 0; u16 w; if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) && (d->dev->dev != 0 || d->dev->func != 0))) { + /* Link Capabilities 2 was reserved before PCIe r3.0 */ + l = get_conf_long(d, where + PCI_EXP_LNKCAP2); + if (l) { + printf("\t\tLnkCap2: Supported Link Speeds: %s, Crosslink%c " + "Retimer%c 2Retimers%c DRS%c\n", + cap_express_link2_speed_cap(PCI_EXP_LNKCAP2_SPEED(l)), + FLAG(l, PCI_EXP_LNKCAP2_CROSSLINK), + FLAG(l, PCI_EXP_LNKCAP2_RETIMER), + FLAG(l, PCI_EXP_LNKCAP2_2RETIMERS), + FLAG(l, PCI_EXP_LNKCAP2_DRS)); + } + w = get_conf_word(d, where + PCI_EXP_LNKCTL2); printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c", cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)), @@ -1227,13 +1304,25 @@ static void cap_express_link2(struct device *d, int where, int type) w = get_conf_word(d, where + PCI_EXP_LNKSTA2); printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n" - "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n", + "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n" + "\t\t\t Retimer%c 2Retimers%c CrosslinkRes: %s", cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)), FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP), FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1), FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2), FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3), - FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ)); + FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ), + FLAG(w, PCI_EXP_LINKSTA2_RETIMER), + FLAG(w, PCI_EXP_LINKSTA2_2RETIMERS), + cap_express_link2_crosslink_res(PCI_EXP_LINKSTA2_CROSSLINK(w))); + + if (exp_downstream_port(type) && (l & PCI_EXP_LNKCAP2_DRS)) { + printf(", DRS%c\n" + "\t\t\t DownstreamComp: %s\n", + FLAG(w, PCI_EXP_LINKSTA2_DRS_RCVD), + cap_express_link2_component(PCI_EXP_LINKSTA2_COMPONENT(w))); + } else + printf("\n"); } static void cap_express_slot2(struct device *d UNUSED, int where UNUSED) diff --git a/tests/cap-exp-lnkcap2 b/tests/cap-exp-lnkcap2 new file mode 100644 index 0000000..d7b159c --- /dev/null +++ b/tests/cap-exp-lnkcap2 @@ -0,0 +1,1317 @@ +00:1c.0 PCI bridge: Intel Corporation Sunrise Point-LP PCI Express Root Port #1 (rev f1) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 256 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 256 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- + LnkCap: Port #1, Speed 8GT/s, Width x4, ASPM not supported + ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 8GT/s (ok), Width x4 (ok) + TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- + Slot #0, PowerLimit 25.000W; Interlock- NoCompl+ + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- + Changed: MRL- PresDet+ LinkState+ + RootCap: CRSVisible- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + DevCap2: Completion Timeout: Range ABC, TimeoutDis+, NROPrPrP-, LTR+ + 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix- + EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- + FRS-, LN System CLS Not Supported, TPHComp-, ExtTPHComp-, ARIFwd+ + AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS- + DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- + AtomicOpsCtl: ReqEn- EgressBlck- + LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- DRS- + LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- + Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- + Compliance De-emphasis: -6dB + LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+, EqualizationPhase1+ + EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee00238 Data: 0000 + Capabilities: [90] Subsystem: Lenovo Device 225a + Capabilities: [a0] Power Management version 3 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Advanced Error Reporting + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt+ RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UESvrt: DLP+ SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ + AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- + HeaderLog: 00000000 00000000 00000000 00000000 + RootCmd: CERptEn- NFERptEn- FERptEn- + RootSta: CERcvd- MultCERcvd- UERcvd- MultUERcvd- + FirstFatal- NonFatalMsg- FatalMsg- IntMsg 0 + ErrorSrc: ERR_COR: 0000 ERR_FATAL/NONFATAL: 0000 + Capabilities: [140 v1] Access Control Services + ACSCap: SrcValid+ TransBlk+ ReqRedir+ CmpltRedir+ UpstreamFwd- EgressCtrl- DirectTrans- + ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- + Capabilities: [200 v1] L1 PM Substates + L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ + PortCommonModeRestoreTime=40us PortTPowerOnTime=44us + L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ + T_CommonMode=255us LTR1.2_Threshold=163840ns + L1SubCtl2: T_PwrOn=44us + Capabilities: [220 v1] Secondary PCI Express + LnkCtl3: LnkEquIntrruptEn-, PerformEqu- + LaneErrStat: 0 +00: 86 80 10 9d 07 04 10 00 f1 00 04 06 00 00 81 00 +10: 00 00 00 00 00 00 00 00 00 02 02 00 d0 d0 00 20 +20: 00 e8 f0 e8 01 70 f1 81 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 ff 01 02 00 +40: 10 80 42 01 01 80 00 00 20 00 10 00 43 40 72 01 +50: 40 00 43 70 00 fd 04 00 00 00 48 01 08 00 00 00 +60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00 +70: 03 00 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 38 02 e0 fe 00 00 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 5a 22 00 00 00 00 00 00 00 00 +a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 11 10 00 07 42 18 00 00 08 00 9e 09 00 00 00 00 +e0: 00 f7 f3 00 00 00 00 00 06 80 12 00 00 00 00 00 +f0: 50 01 00 00 00 03 00 40 b3 0f 41 08 04 c0 00 01 +100: 01 00 01 14 00 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GP108M [GeForce MX150] (rev a1) + Subsystem: Lenovo Device 225b + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- + Capabilities: [420 v2] Advanced Error Reporting + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ + AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- + HeaderLog: 00000000 00000000 00000000 00000000 + Capabilities: [600 v1] Vendor Specific Information: ID=0001 Rev=1 Len=024 + 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00 00 +ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +08:00.0 PCI bridge: Intel Corporation JHL6240 Thunderbolt 3 Bridge (Low Power) [Alpine Ridge LP 2016] (rev 01) (prog-if 00 [Normal decode]) + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [80] Power Management version 3 + Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+) + Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [88] MSI: Enable+ Count=1/1 Maskable- 64bit+ + Address: 00000000fee002b8 Data: 0000 + Capabilities: [ac] Subsystem: Device 2222:1111 + Capabilities: [c0] Express (v2) Downstream Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag+ RBE+ + DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq- + RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ + MaxPayload 128 bytes, MaxReadReq 512 bytes + DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr+ TransPend- + LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <2us, L1 <4us + ClockPM- Surprise- LLActRep- BwNot+ ASPMOptComp+ + LnkCtl: ASPM Disabled; Disabled- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s (ok), Width x4 (ok) + TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise- + Slot #0, PowerLimit 0.000W; Interlock- NoCompl+ + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- + Changed: MRL- PresDet+ LinkState- + DevCap2: Completion Timeout: Not Supported, TimeoutDis-, NROPrPrP-, LTR+ + 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix- + EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- + FRS-, ARIFwd- + AtomicOpsCap: Routing- + DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd- + AtomicOpsCtl: EgressBlck- + LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- DRS- + LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB + Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- + Compliance De-emphasis: -6dB + LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1- + EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest- + Capabilities: [100 v1] Device Serial Number 21-df-cc-fa-34-c9-a0-00 + Capabilities: [200 v1] Advanced Error Reporting + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UESvrt: DLP+ SDES- TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr- + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ + AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- + HeaderLog: 00000000 00000000 00000000 00000000 + Capabilities: [300 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed- WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + Capabilities: [400 v1] Power Budgeting + Capabilities: [500 v1] Vendor Specific Information: ID=1234 Rev=1 Len=0e0 + Capabilities: [700 v1] Secondary PCI Express + LnkCtl3: LnkEquIntrruptEn-, PerformEqu- + LaneErrStat: 0 +00: 86 80 c0 15 06 04 10 00 01 00 04 06 20 00 01 00 +10: 00 00 00 00 00 00 00 00 08 09 09 00 f1 01 00 00 +20: 00 e6 00 e6 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 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Vendor Specific Information: ID=1234 Rev=1 Len=088 + Capabilities: [600 v1] Latency Tolerance Reporting + Max snoop latency: 3145728ns + Max no snoop latency: 3145728ns +00: 86 80 bf 15 06 04 10 00 01 00 80 08 20 00 00 00 +10: 00 00 00 e6 00 00 04 e6 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 22 22 11 11 +30: 00 00 00 00 80 00 00 00 00 00 00 00 ff 01 00 00 +40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 01 88 c3 ff 08 00 00 00 05 c0 80 00 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 11 00 0f 80 01 00 00 00 a1 0f 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 10 a0 02 00 a0 87 00 00 10 29 10 00 41 5c 05 00 +d0: 40 01 41 10 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 12 08 00 00 00 04 00 00 00 00 00 00 +f0: 00 00 01 00 00 00 00 00 00 00 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