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[4/8] PCI: aardvark: Do not overwrite Link Status register and ASPM Control bits in Link Control register

Message ID 20200415160054.951-5-pali@kernel.org
State New
Headers show
Series PCI: aardvark: Fix support for Turris MOX and Compex wifi cards | expand

Commit Message

Pali Rohár April 15, 2020, 4 p.m. UTC
Trying to overwrite or change Link Status register does not have any
effect as this is read-only register. Trying to overwrite bits for
Negotiated Link Width value in Link Status register does not make sense.
So remove code which is doing it.

In future proper change of link width can be done via Lane Count Select
bits in PCIe Control 0 register.

Trying to unconditionally enable ASPM L0s via ASPM Control bits in Link
Control register is wrong. There should be at least some detection if
endpoint supports L0s as support for it is not mandatory.

Moreover ASPM Control bits in Link Control register are controlled by
pcie/aspm.c code which sets it according to system ASPM settings,
immediately after aardvark driver probe callback finish. So setting these
bits by aardvark driver has no long running effect.

So remove code which touches ASPM L0s bits from aardvark driver and let
kernel's ASPM implementation to set ASPM state properly.

Some users are reporting issues that this code which unconditionally set
ASPM L0s bits in Link Control register is problematic for some Intel wifi
cards. And disabling that code fixes support for those cards. See e.g.:
https://bugzilla.kernel.org/show_bug.cgi?id=196339

If problem with Intel wifi cards occur also after this commit then driver
independent pcie/aspm.c code could be modified / hooked to not enable ASPM
L0s state for affected problematic cards.

Signed-off-by: Pali Rohár <pali@kernel.org>
---
 drivers/pci/controller/pci-aardvark.c | 4 ----
 1 file changed, 4 deletions(-)
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Patch

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 756b31c4d20b..02c69fc9aadf 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -380,10 +380,6 @@  static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 
 	advk_pcie_wait_for_link(pcie);
 
-	reg = PCIE_CORE_LINK_L0S_ENTRY |
-		(1 << PCIE_CORE_LINK_WIDTH_SHIFT);
-	advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
-
 	reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
 	reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
 		PCIE_CORE_CMD_IO_ACCESS_EN |