From patchwork Mon Feb 24 16:58:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Philippe Brucker X-Patchwork-Id: 1243319 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=jR7RaN40; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 48R7ZP70Rxz9sRf for ; Tue, 25 Feb 2020 03:59:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728040AbgBXQ7I (ORCPT ); Mon, 24 Feb 2020 11:59:08 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:43670 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727644AbgBXQ7G (ORCPT ); Mon, 24 Feb 2020 11:59:06 -0500 Received: by mail-wr1-f67.google.com with SMTP id r11so11240639wrq.10 for ; Mon, 24 Feb 2020 08:59:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L9Q0qcxnkV13c6MhKRP3gkBpAW/Xjj6KTCyBYPPUbo8=; b=jR7RaN40drIO3Z8YN3DdhMKXNAVqDCtLzCnR6gbvLpVA/Aln4pckiC3TMYCvU/Hr3o ijNGM9EOE+8fOESdkaILMtKqGiSU3jxQlhAv81EPv1g4giBq6E+GNU9NF1XS9+XUxqpv Z1Y4k7JAjRn6JCf0HnoMAAsuLrLx6R7gc8PnPUB807vFu6YF2Gv6Cus2I62H+2DXg+OJ rMbRmUuc/BfoBIRbQ6OS0ujUx/hVsYU5Y7neAAcunsZuxM7GhpXI1pYohEA6mlYujQSE 0aaoLw1BVr7jMCzsX+NBL8CH7zND4vxqR9LRD4eFmI21ORXyI1FeB/gv0pyptSkP+kjp 0bjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L9Q0qcxnkV13c6MhKRP3gkBpAW/Xjj6KTCyBYPPUbo8=; b=uHMS23LttQzfikPOkr0x06mTURxZMeKPzIoieFjT8hAYYEgnXCMys16BK0C52c7fPS Ek2wk9XQ92IOkstHAZ8q6LQyH0nsaD4iaxmFW/T29S/+VQ6HjuTmN229CsEHf2I4O8HX 9DsYrSRr91KJ9EbmfwfgLAmvIytHsnRhoATYN6ZFEG7iTpWcArkeT+5NjTI+HPOiEsN0 ZH4Fvt+XOp0OvzjENFZm5opFplZay60qPWEGfliL+vZR7RB08NTldaLI9nbkHIbeHYmi 3sKV+2FORkspcvBGoaOjFaJQpN1DHNiY9W8h7QyUDcD6YL5uDIZfhL1xdCPquAPyrPKO Y1cA== X-Gm-Message-State: APjAAAVX5eFJ8IZ2e26vO3yWAX/viJXtCsk/fHcP8afCq9k4YcwPZl4C ljoWlOc720hzCM4X6Fqi54NJzVVnGFo= X-Google-Smtp-Source: APXvYqwBvkXYS+FZhWNBv6R7Dnf8ywFoid6nCAlXnksnCN/yapBQ30GW0ZCSqCk1G3DmpN0THhlTRg== X-Received: by 2002:a5d:4f89:: with SMTP id d9mr67669582wru.391.1582563544022; Mon, 24 Feb 2020 08:59:04 -0800 (PST) Received: from localhost.localdomain ([2001:171b:c9a8:fbc0:116c:c27a:3e7f:5eaf]) by smtp.gmail.com with ESMTPSA id b10sm19473978wrt.90.2020.02.24.08.59.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 08:59:03 -0800 (PST) From: Jean-Philippe Brucker To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, will@kernel.org, bhelgaas@google.com Cc: joro@8bytes.org, robin.murphy@arm.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, robh@kernel.org Subject: [PATCH v2 2/6] iommu/arm-smmu-v3: Add support for PCI PASID Date: Mon, 24 Feb 2020 17:58:42 +0100 Message-Id: <20200224165846.345993-3-jean-philippe@linaro.org> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200224165846.345993-1-jean-philippe@linaro.org> References: <20200224165846.345993-1-jean-philippe@linaro.org> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Enable PASID for PCI devices that support it. Initialize PASID early in add_device() because it must be enabled before ATS. Tested-by: Zhangfei Gao Reviewed-by: Jonathan Cameron Signed-off-by: Jean-Philippe Brucker --- drivers/iommu/arm-smmu-v3.c | 62 ++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index aa3ac2a03807..6b76df37025e 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2628,6 +2628,53 @@ static void arm_smmu_disable_ats(struct arm_smmu_master *master) atomic_dec(&smmu_domain->nr_ats_masters); } +static int arm_smmu_enable_pasid(struct arm_smmu_master *master) +{ + int ret; + int features; + int num_pasids; + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return -ENODEV; + + pdev = to_pci_dev(master->dev); + + features = pci_pasid_features(pdev); + if (features < 0) + return features; + + num_pasids = pci_max_pasids(pdev); + if (num_pasids <= 0) + return num_pasids; + + ret = pci_enable_pasid(pdev, features); + if (ret) { + dev_err(&pdev->dev, "Failed to enable PASID\n"); + return ret; + } + + master->ssid_bits = min_t(u8, ilog2(num_pasids), + master->smmu->ssid_bits); + return 0; +} + +static void arm_smmu_disable_pasid(struct arm_smmu_master *master) +{ + struct pci_dev *pdev; + + if (!dev_is_pci(master->dev)) + return; + + pdev = to_pci_dev(master->dev); + + if (!pdev->pasid_enabled) + return; + + master->ssid_bits = 0; + pci_disable_pasid(pdev); +} + static void arm_smmu_detach_dev(struct arm_smmu_master *master) { unsigned long flags; @@ -2831,13 +2878,23 @@ static int arm_smmu_add_device(struct device *dev) master->ssid_bits = min(smmu->ssid_bits, fwspec->num_pasid_bits); + /* + * Note that PASID must be enabled before, and disabled after ATS: + * PCI Express Base 4.0r1.0 - 10.5.1.3 ATS Control Register + * + * Behavior is undefined if this bit is Set and the value of the PASID + * Enable, Execute Requested Enable, or Privileged Mode Requested bits + * are changed. + */ + arm_smmu_enable_pasid(master); + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) master->ssid_bits = min_t(u8, master->ssid_bits, CTXDESC_LINEAR_CDMAX); ret = iommu_device_link(&smmu->iommu, dev); if (ret) - goto err_free_master; + goto err_disable_pasid; group = iommu_group_get_for_dev(dev); if (IS_ERR(group)) { @@ -2850,6 +2907,8 @@ static int arm_smmu_add_device(struct device *dev) err_unlink: iommu_device_unlink(&smmu->iommu, dev); +err_disable_pasid: + arm_smmu_disable_pasid(master); err_free_master: kfree(master); fwspec->iommu_priv = NULL; @@ -2870,6 +2929,7 @@ static void arm_smmu_remove_device(struct device *dev) arm_smmu_detach_dev(master); iommu_group_remove_device(dev); iommu_device_unlink(&smmu->iommu, dev); + arm_smmu_disable_pasid(master); kfree(master); iommu_fwspec_free(dev); }