| Message ID | 20200213040644.45858-14-Zhiqiang.Hou@nxp.com |
|---|---|
| State | New |
| Headers | show
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Thu, 13 Feb 2020 04:11:03 +0000 From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com> To: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, andrew.murray@arm.com, arnd@arndb.de, mark.rutland@arm.com, l.subrahmanya@mobiveil.co.in, shawnguo@kernel.org, m.karthikeyan@mobiveil.co.in, leoyang.li@nxp.com, lorenzo.pieralisi@arm.com, catalin.marinas@arm.com, will.deacon@arm.com Cc: Mingkai.Hu@nxp.com, Minghuan.Lian@nxp.com, Xiaowei.Bao@nxp.com, Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Subject: [PATCHv10 13/13] arm64: defconfig: Enable CONFIG_PCIE_LAYERSCAPE_GEN4 Date: Thu, 13 Feb 2020 12:06:44 +0800 Message-Id: <20200213040644.45858-14-Zhiqiang.Hou@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200213040644.45858-1-Zhiqiang.Hou@nxp.com> References: <20200213040644.45858-1-Zhiqiang.Hou@nxp.com> Content-Type: text/plain X-ClientProxiedBy: HK2PR04CA0069.apcprd04.prod.outlook.com (2603:1096:202:15::13) To DB8PR04MB6747.eurprd04.prod.outlook.com (2603:10a6:10:10b::31) MIME-Version: 1.0 Received: from localhost.localdomain (119.31.174.73) by HK2PR04CA0069.apcprd04.prod.outlook.com (2603:1096:202:15::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2729.24 via Frontend Transport; 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PCI: Recode Mobiveil driver and add PCIe Gen4 driver for NXP Layerscape SoCs
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On Thu, Feb 13, 2020 at 12:06:44PM +0800, Zhiqiang Hou wrote: > From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > > Enable the PCIe Gen4 controller driver for Layerscape SoCs. > > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> > Reviewed-by: Minghuan Lian <Minghuan.Lian@nxp.com> Applied, thanks.
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 4631a1190719..3bbd14e9dfd5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -195,6 +195,7 @@ CONFIG_PCI_HOST_THUNDER_ECAM=y CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCIE_BRCMSTB=m CONFIG_PCI_LAYERSCAPE=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCI_HISI=y CONFIG_PCIE_QCOM=y CONFIG_PCIE_ARMADA_8K=y