From patchwork Mon Jul 1 12:40:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1125280 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="iV3APRVP"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45cn6S6lR5z9sPM for ; Mon, 1 Jul 2019 22:41:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727898AbfGAMlD (ORCPT ); Mon, 1 Jul 2019 08:41:03 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:9144 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727564AbfGAMlD (ORCPT ); Mon, 1 Jul 2019 08:41:03 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 01 Jul 2019 05:40:59 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 01 Jul 2019 05:41:01 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 01 Jul 2019 05:41:01 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 1 Jul 2019 12:41:01 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 1 Jul 2019 12:41:01 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 1 Jul 2019 12:41:01 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 01 Jul 2019 05:41:01 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH V12 06/12] dt-bindings: PCI: designware: Add binding for CDM register check Date: Mon, 1 Jul 2019 18:10:04 +0530 Message-ID: <20190701124010.7484-7-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190701124010.7484-1-vidyas@nvidia.com> References: <20190701124010.7484-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1561984859; bh=qaV4xsdH5SZ5f+s7IswQ1pQshcuCt0JZQaiZ7RtG2kc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=iV3APRVPeXEGrLT7iWOlLVtrNYeCAu3Kd2q97bPYdMainzSTHS6XI0zGjKRgtKR9e WZ3AjGppPlbarLnW+HLITxCqKI0aj7cTUSsFuxVIMI3p+CkGnwyDdtwUUFScqnBPXO 5qaqMktvLJcP2qZxf+zFGLtoWsEz7fdNdAb8Vx0ouAWy2B3gT47M9b6vKUaKI5rvw1 qu+CIPrsSEMc53ilYZC6OuT3iXyaA8XCGZI5ys9AyNRLvCgaIsekm2TTXXPaMr1N0C GVbu1RcrTEap8osuXY+OnJMmxEo35Y4AYJHlFjKu1qhmlgWcXQ4aBoHU54v46I+cPj 5XRoVSYehHbDQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add support to enable CDM (Configuration Dependent Module) registers check for any data corruption. CDM registers include standard PCIe configuration space registers, Port Logic registers and iATU and DMA registers. Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook Version 4.90a Signed-off-by: Vidya Sagar Reviewed-by: Thierry Reding Reviewed-by: Rob Herring --- Changes since [v11]: * None Changes since [v10]: * None Changes since [v9]: * None Changes since [v8]: * None Changes since [v7]: * None Changes since [v6]: * Changed "enable-cdm-check" to "snps,enable-cdm-check" Changes since [v5]: * None Changes since [v4]: * None Changes since [v3]: * None Changes since [v2]: * Changed flag name from 'cdm-check' to 'enable-cdm-check' * Added info about Port Logic and DMA registers being part of CDM Changes since [v1]: * This is a new patch in v2 series Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 5561a1c060d0..3fba04da6a59 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -34,6 +34,11 @@ Optional properties: - clock-names: Must include the following entries: - "pcie" - "pcie_bus" +- snps,enable-cdm-check: This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. RC mode: - num-viewport: number of view ports configured in hardware. If a platform does not specify it, the driver assumes 2.