From patchwork Thu Apr 11 17:03:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 1084196 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="VCBnG/S8"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44g6q66fKJz9s0W for ; Fri, 12 Apr 2019 03:05:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726992AbfDKRFh (ORCPT ); Thu, 11 Apr 2019 13:05:37 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:7162 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726585AbfDKRFh (ORCPT ); Thu, 11 Apr 2019 13:05:37 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 11 Apr 2019 10:05:34 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 11 Apr 2019 10:05:36 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 11 Apr 2019 10:05:36 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 11 Apr 2019 17:05:36 +0000 Received: from manikanta-bm2.nvidia.com (172.20.13.39) by HQMAIL.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Thu, 11 Apr 2019 17:05:32 +0000 From: Manikanta Maddireddy To: , , , , , , CC: , , , Manikanta Maddireddy Subject: [PATCH 18/30] PCI: tegra: Change PRSNT_SENSE irq log to debug Date: Thu, 11 Apr 2019 22:33:43 +0530 Message-ID: <20190411170355.6882-19-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190411170355.6882-1-mmaddireddy@nvidia.com> References: <20190411170355.6882-1-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1555002334; bh=9VfDfe5jGU/GmLhYKRipijeH5Cjn62XH8VjLJj+t2H8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=VCBnG/S8OKUwFSjmkrVwXz1OVf3XFOOZaUcHYAsxhwOjqYGz59IEe47WcFSHPfKBI JqH+f58mu/0xDh0PcjNV2L7Bte15TpIQ6SMy+tESA90IyrLAOdAs05KhQ1zIWzRsUh 4ZmYzyxS9id12uNIqjbPiINcbgTUkYKK2NVO+pkPI1vfN8fI4ESp3ZYZnUR1xSS7lx ckRU6N5rDE0WDJB5Cs1Bc3Iceo5Go0q3iEaf39s0lVKjUUFRxC9Wts99ehHX1MkeLS z2FHwoncys7kD+VZ7Tx+qf80Y+fTQstHXNsJogCOr1AiV87mKSejdWx5ww2TPMkpbm dL1yi+CP0/fGQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org PRSNT_MAP bit field is programmed to update the slot present status. PRSNT_SENSE irq is triggered when this bit field is programmed, which is not an error. Add a new switch case to trap RSNT_SENSE code and print it with debug log level. Signed-off-by: Manikanta Maddireddy --- drivers/pci/controller/pci-tegra.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index cf2715065a53..dcfe97711cb5 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -855,6 +855,9 @@ static irqreturn_t tegra_pcie_isr(int irq, void *arg) switch (code) { case AFI_INTR_LEGACY: return IRQ_NONE; + case AFI_INTR_PE_PRSNT_SENSE: + dev_dbg(dev, "%s, signature: %08x\n", err_msg[code], signature); + break; /* * do not pollute kernel log with master abort reports since they * happen a lot during enumeration