diff mbox series

[v2,2/7] dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY

Message ID 20190219060407.15263-3-bjorn.andersson@linaro.org
State Changes Requested
Delegated to: Lorenzo Pieralisi
Headers show
Series QCS404 PCIe PHY and controller | expand

Commit Message

Bjorn Andersson Feb. 19, 2019, 6:04 a.m. UTC 
The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of
Qualcomm platforms, add a binding to describe this.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
 .../bindings/phy/qcom-pcie2-phy.txt           | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt

Comments

Rob Herring Feb. 22, 2019, 7:57 p.m. UTC | #1 
On Mon, Feb 18, 2019 at 10:04:02PM -0800, Bjorn Andersson wrote:
> The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of
> Qualcomm platforms, add a binding to describe this.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>  .../bindings/phy/qcom-pcie2-phy.txt           | 40 +++++++++++++++++++
>  1 file changed, 40 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> new file mode 100644
> index 000000000000..7da02f9d78c7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> @@ -0,0 +1,40 @@
> +Qualcomm PCIe2 PHY controller
> +=============================
> +
> +The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
> +platforms.
> +
> +Required properties:
> + - compatible: compatible list, should be:
> +	       "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
> +
> + - reg: offset and length of the PHY register set.
> + - #phy-cells: must be 0.
> +
> + - clocks: a clock-specifier pair for the "pipe" clock
> +
> + - vdda-vp-supply: phandle to low voltage regulator
> + - vdda-vph-supply: phandle to high voltage regulator
> +
> + - resets: reset-specifier pairs for the "phy" and "pipe" resets
> + - reset-names: list of resets, should contain:
> +		"phy" and "pipe"
> +
> + - clock-output-names: name of the outgoing clock signal from the PHY PLL

Not valid to have this without '#clock-cells'.

Though I'm confused how this and the input clock name seem to match.

> +
> +Example:
> + phy@7786000 {
> +	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
> +	reg = <0x07786000 0xb8>;
> +
> +	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> +	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
> +	         <&gcc GCC_PCIE_0_PIPE_ARES>;
> +	reset-names = "phy", "pipe";
> +
> +	vdda-vp-supply = <&vreg_l3_1p05>;
> +	vdda-vph-supply = <&vreg_l5_1p8>;
> +
> +	clock-output-names = "pcie_0_pipe_clk";
> +	#phy-cells = <0>;
> + };
> -- 
> 2.18.0
>
Bjorn Andersson Feb. 27, 2019, 4:25 a.m. UTC | #2 
On Fri 22 Feb 11:57 PST 2019, Rob Herring wrote:

> On Mon, Feb 18, 2019 at 10:04:02PM -0800, Bjorn Andersson wrote:
> > The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of
> > Qualcomm platforms, add a binding to describe this.
> > 
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> >  .../bindings/phy/qcom-pcie2-phy.txt           | 40 +++++++++++++++++++
> >  1 file changed, 40 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> > new file mode 100644
> > index 000000000000..7da02f9d78c7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> > @@ -0,0 +1,40 @@
> > +Qualcomm PCIe2 PHY controller
> > +=============================
> > +
> > +The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
> > +platforms.
> > +
> > +Required properties:
> > + - compatible: compatible list, should be:
> > +	       "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
> > +
> > + - reg: offset and length of the PHY register set.
> > + - #phy-cells: must be 0.
> > +
> > + - clocks: a clock-specifier pair for the "pipe" clock
> > +
> > + - vdda-vp-supply: phandle to low voltage regulator
> > + - vdda-vph-supply: phandle to high voltage regulator
> > +
> > + - resets: reset-specifier pairs for the "phy" and "pipe" resets
> > + - reset-names: list of resets, should contain:
> > +		"phy" and "pipe"
> > +
> > + - clock-output-names: name of the outgoing clock signal from the PHY PLL
> 
> Not valid to have this without '#clock-cells'.
> 

This happens to work today as we don't describe &gcc's dependency on
this, but just rely on the global clock namespace. But it should be
there, so I'll respin this.

> Though I'm confused how this and the input clock name seem to match.
> 

The PHY generates the clock we call "pcie_0_pipe_clk" which is fed into
the global clock controller (gcc), where it can be gated (and divided)
and then fed back to both the PHY and the controller as
"gcc_pcie_0_pipe_clk".


Thanks for the review Rob.

Regards,
Bjorn

> > +
> > +Example:
> > + phy@7786000 {
> > +	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
> > +	reg = <0x07786000 0xb8>;
> > +
> > +	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> > +	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
> > +	         <&gcc GCC_PCIE_0_PIPE_ARES>;
> > +	reset-names = "phy", "pipe";
> > +
> > +	vdda-vp-supply = <&vreg_l3_1p05>;
> > +	vdda-vph-supply = <&vreg_l5_1p8>;
> > +
> > +	clock-output-names = "pcie_0_pipe_clk";
> > +	#phy-cells = <0>;
> > + };
> > -- 
> > 2.18.0
> >
Lorenzo Pieralisi April 1, 2019, 2:58 p.m. UTC | #3 
On Tue, Feb 26, 2019 at 08:25:45PM -0800, Bjorn Andersson wrote:
> On Fri 22 Feb 11:57 PST 2019, Rob Herring wrote:
> 
> > On Mon, Feb 18, 2019 at 10:04:02PM -0800, Bjorn Andersson wrote:
> > > The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of
> > > Qualcomm platforms, add a binding to describe this.
> > > 
> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > ---
> > >  .../bindings/phy/qcom-pcie2-phy.txt           | 40 +++++++++++++++++++
> > >  1 file changed, 40 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> > > 
> > > diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> > > new file mode 100644
> > > index 000000000000..7da02f9d78c7
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
> > > @@ -0,0 +1,40 @@
> > > +Qualcomm PCIe2 PHY controller
> > > +=============================
> > > +
> > > +The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
> > > +platforms.
> > > +
> > > +Required properties:
> > > + - compatible: compatible list, should be:
> > > +	       "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
> > > +
> > > + - reg: offset and length of the PHY register set.
> > > + - #phy-cells: must be 0.
> > > +
> > > + - clocks: a clock-specifier pair for the "pipe" clock
> > > +
> > > + - vdda-vp-supply: phandle to low voltage regulator
> > > + - vdda-vph-supply: phandle to high voltage regulator
> > > +
> > > + - resets: reset-specifier pairs for the "phy" and "pipe" resets
> > > + - reset-names: list of resets, should contain:
> > > +		"phy" and "pipe"
> > > +
> > > + - clock-output-names: name of the outgoing clock signal from the PHY PLL
> > 
> > Not valid to have this without '#clock-cells'.
> > 
> 
> This happens to work today as we don't describe &gcc's dependency on
> this, but just rely on the global clock namespace. But it should be
> there, so I'll respin this.

Should I drop this series from the PCI queue waiting for v3 then ?

Thanks,
Lorenzo

> > Though I'm confused how this and the input clock name seem to match.
> > 
> 
> The PHY generates the clock we call "pcie_0_pipe_clk" which is fed into
> the global clock controller (gcc), where it can be gated (and divided)
> and then fed back to both the PHY and the controller as
> "gcc_pcie_0_pipe_clk".
> 
> 
> Thanks for the review Rob.
> 
> Regards,
> Bjorn
> 
> > > +
> > > +Example:
> > > + phy@7786000 {
> > > +	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
> > > +	reg = <0x07786000 0xb8>;
> > > +
> > > +	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
> > > +	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
> > > +	         <&gcc GCC_PCIE_0_PIPE_ARES>;
> > > +	reset-names = "phy", "pipe";
> > > +
> > > +	vdda-vp-supply = <&vreg_l3_1p05>;
> > > +	vdda-vph-supply = <&vreg_l5_1p8>;
> > > +
> > > +	clock-output-names = "pcie_0_pipe_clk";
> > > +	#phy-cells = <0>;
> > > + };
> > > -- 
> > > 2.18.0
> > >
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
new file mode 100644
index 000000000000..7da02f9d78c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt
@@ -0,0 +1,40 @@ 
+Qualcomm PCIe2 PHY controller
+=============================
+
+The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
+platforms.
+
+Required properties:
+ - compatible: compatible list, should be:
+	       "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
+
+ - reg: offset and length of the PHY register set.
+ - #phy-cells: must be 0.
+
+ - clocks: a clock-specifier pair for the "pipe" clock
+
+ - vdda-vp-supply: phandle to low voltage regulator
+ - vdda-vph-supply: phandle to high voltage regulator
+
+ - resets: reset-specifier pairs for the "phy" and "pipe" resets
+ - reset-names: list of resets, should contain:
+		"phy" and "pipe"
+
+ - clock-output-names: name of the outgoing clock signal from the PHY PLL
+
+Example:
+ phy@7786000 {
+	compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
+	reg = <0x07786000 0xb8>;
+
+	clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+	resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
+	         <&gcc GCC_PCIE_0_PIPE_ARES>;
+	reset-names = "phy", "pipe";
+
+	vdda-vp-supply = <&vreg_l3_1p05>;
+	vdda-vph-supply = <&vreg_l5_1p8>;
+
+	clock-output-names = "pcie_0_pipe_clk";
+	#phy-cells = <0>;
+ };