| Message ID | 20181206073545.10967-3-andrew.smirnov@gmail.com |
|---|---|
| State | Accepted |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | PCIE support for i.MX8MQ | expand |
Am Mittwoch, den 05.12.2018, 23:35 -0800 schrieb Andrey Smirnov: > PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family, > so none of the code in current implementation of imx6_pcie_reset_phy() > is applicable. > > Cc: bhelgaas@google.com > > Cc: Fabio Estevam <fabio.estevam@nxp.com> > Cc: cphealy@gmail.com > Cc: l.stach@pengutronix.de > > Cc: Leonard Crestez <leonard.crestez@nxp.com> > > Cc: "A.s. Dong" <aisheng.dong@nxp.com> > > Cc: Richard Zhu <hongxing.zhu@nxp.com> > Cc: linux-imx@nxp.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-pci@vger.kernel.org > > Tested-by: Trent Piepho <tpiepho@impinj.com> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/pci/controller/dwc/pci-imx6.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index c140f7987598..3c3002861d25 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -245,6 +245,9 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) > { > > u32 tmp; > > > + if (imx6_pcie->variant == IMX7D) > > + return; > + > > pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); > > tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | > > PHY_RX_OVRD_IN_LO_RX_PLL_EN);
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index c140f7987598..3c3002861d25 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -245,6 +245,9 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) { u32 tmp; + if (imx6_pcie->variant == IMX7D) + return; + pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN);