From patchwork Fri Oct 6 16:39:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 822580 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ByhmfIU+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7wND2f2Nz9t4b for ; Sat, 7 Oct 2017 03:39:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751423AbdJFQjz (ORCPT ); Fri, 6 Oct 2017 12:39:55 -0400 Received: from mail-wm0-f43.google.com ([74.125.82.43]:44191 "EHLO mail-wm0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751528AbdJFQjv (ORCPT ); Fri, 6 Oct 2017 12:39:51 -0400 Received: by mail-wm0-f43.google.com with SMTP id 196so3292065wma.1 for ; Fri, 06 Oct 2017 09:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4D8J4X59CFYhIaQncuIXv1e01SjU+/ZZUbj0qDqaxsM=; b=ByhmfIU+WD5SnLUFznLaNTgiahOHa8wlGs4xacpK8AI8Q2/ejBv4eKFAnK6YIhM8/3 AMn3TXfmVtlGj3u+NCdOMt80IiBpTxji7S4rZlt+8oSEypGwGyUQjnhIHnvVqu7jjgwh qtpg1xYSFiQU+0VBjk3jG2XXkbZo2CKa8aWns= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4D8J4X59CFYhIaQncuIXv1e01SjU+/ZZUbj0qDqaxsM=; b=m2Glgcd1gx2LyMk73wHyPiLs5PNThAmhtLVj5/5IsNRk4xcWrh5eXW3rf8z7+TDpQP uklotMx2el7DoLikpydWIPskvziRKJ76I//GHym01TG74z42HQcwRvRO8NUGViHnuO5N 0Uv9nKL3G4yEiiHoH/Qfb7oWQ/BTnaJGkFZEQQ5P5CkOFg5y5gQGMGAwhOP0w6KPBpSz OVsdakw+qw8m/L2iUxcdST/5DoXmY/Y1D80cHiPWvquF3RSB4kePbLlRlgDbpYvKxgQ4 ZUwqpQculxHh4DXeZ9Qzxt8L1XFxIiYTWqvZLnWwf12jcIWOx6mgkplnyo82+ZvsGZ/B VkWg== X-Gm-Message-State: AMCzsaWNvGe0IZQUQmYasJosrIXF2xxq9VhMFhJpkWbc3p7is9r53PCd ao+N3bj9O3oFhY3o8km15uw+K87p50s= X-Google-Smtp-Source: AOwi7QCzSn8iy5P/7XRazeOGIKAxaqYb1tRHqwkMe8lV2d9R0EbDok3R5P7mQSzjkENGA2atG80Ujg== X-Received: by 10.28.236.25 with SMTP id k25mr2457861wmh.146.1507307990423; Fri, 06 Oct 2017 09:39:50 -0700 (PDT) Received: from localhost.localdomain ([160.90.203.54]) by smtp.gmail.com with ESMTPSA id b190sm2873023wma.41.2017.10.06.09.39.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 09:39:49 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Bjorn Helgaas , Rob Herring , Will Deacon Subject: [PATCH v4 2/2] dt-bindings: designware: add binding for Designware PCIe in ECAM mode Date: Fri, 6 Oct 2017 17:39:19 +0100 Message-Id: <20171006163919.14898-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006163919.14898-1-ard.biesheuvel@linaro.org> References: <20171006163919.14898-1-ard.biesheuvel@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Describe the binding for firmware-configured instances of the Synopsys DesignWare PCIe controller in RC mode, that are almost but not quite ECAM compliant. Acked-by: Rob Herring Signed-off-by: Ard Biesheuvel --- Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt | 42 ++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt new file mode 100644 index 000000000000..515b2f9542e5 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt @@ -0,0 +1,42 @@ +* Synopsys DesignWare PCIe root complex in ECAM shift mode + +In some cases, firmware may already have configured the Synopsys DesignWare +PCIe controller in RC mode with static ATU window mappings that cover all +config, MMIO and I/O spaces in a [mostly] ECAM compatible fashion. +In this case, there is no need for the OS to perform any low level setup +of clocks, PHYs or device registers, nor is there any reason for the driver +to reconfigure ATU windows for config and/or IO space accesses at runtime. + +In cases where the IP was synthesized with a minimum ATU window size of +64 KB, it cannot be supported by the generic ECAM driver, because it +requires special config space accessors that filter accesses to device #1 +and beyond on the first bus. + +Required properties: +- compatible: "marvell,armada8k-pcie-ecam" or + "socionext,synquacer-pcie-ecam" or + "snps,dw-pcie-ecam" (must be preceded by a more specific match) + +Please refer to the binding document of "pci-host-ecam-generic" in the +file host-generic-pci.txt for a description of the remaining required +and optional properties. + +Example: + + pcie1: pcie@7f000000 { + compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam"; + device_type = "pci"; + reg = <0x0 0x7f000000 0x0 0xf00000>; + bus-range = <0x0 0xe>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>, + <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>, + <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>; + + #interrupt-cells = <0x1>; + interrupt-map-mask = <0x0 0x0 0x0 0x0>; + interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 0x0 182 0x4>; + msi-map = <0x0 &its 0x0 0x10000>; + dma-coherent; + };