From patchwork Fri Oct 6 16:39:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 822581 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="HqPUzMLk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3y7wNh4yKhz9t5c for ; Sat, 7 Oct 2017 03:40:20 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752395AbdJFQjy (ORCPT ); Fri, 6 Oct 2017 12:39:54 -0400 Received: from mail-wm0-f54.google.com ([74.125.82.54]:48116 "EHLO mail-wm0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751654AbdJFQjt (ORCPT ); Fri, 6 Oct 2017 12:39:49 -0400 Received: by mail-wm0-f54.google.com with SMTP id t69so8608446wmt.2 for ; Fri, 06 Oct 2017 09:39:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VnLcXa3a4OXL5SHoEMnGS9xOO1BWa1UfDZrAGpOINeE=; b=HqPUzMLkPUjbbolFPamK7kEl2IX+Wt3rqAvKqSMFYKT9OvyJ1K7afXtj9hnEP07YpG fHTAbtF7K+dT477WbM4MxkNeQqlPaji9UHAWSNF1/v5BTkUsqiKhHkh8Po0z202jE3LA 3Uw0pGp/CWDxq0R8GqApzbYKzwY2VAhRGjRlg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VnLcXa3a4OXL5SHoEMnGS9xOO1BWa1UfDZrAGpOINeE=; b=WSNN9d4DE27FDyIS3xqVc/b6kWqkLmKxXQ50EHUkAJiXfbXB1PqaQHXOcYt/Hjo5/T b+MgyEkcgVUtVAi2E9k/P8TQno+lfiVZpCu2DfSnTMrtw9cs3REqRg4LXtU79iaDzERi wvjkjjSD9s8EgI4Qs142APNytULPbPaRkjZM3qNfORmGkp4n/pbMTHe/Szi5PkP+Au1T dYbO9MDT0IUMU/8egE1Qk3w1Q6FtIxR71B9bqt5h6CYHhGUcLBcXZtQyKE/qqcsfjjGA pQ8G8m1W5865ZQBME3g3b89V3eLfHNLSmBDLOu1f28Y6LhqW8ggOtkOtHXVu2Q8+uKND SqqQ== X-Gm-Message-State: AMCzsaUSR8IMMatmcWEcZSU0EEQ18NwSnKi2mC2Czexbv3ZiJQT8GEWn 0F2w1kL3yYAsF/9GHz/xngQJi+T7eG0= X-Google-Smtp-Source: AOwi7QCxEexl4Xpo6u6VGEpNDQp7glKH58Wv7ZZHSp0RTwj5624iHRT/tDyqWneckvetvPVE3jFN7A== X-Received: by 10.28.156.67 with SMTP id f64mr2160131wme.42.1507307988162; Fri, 06 Oct 2017 09:39:48 -0700 (PDT) Received: from localhost.localdomain ([160.90.203.54]) by smtp.gmail.com with ESMTPSA id b190sm2873023wma.41.2017.10.06.09.39.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Oct 2017 09:39:45 -0700 (PDT) From: Ard Biesheuvel To: linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Leif Lindholm , Graeme Gregory , Bjorn Helgaas , Rob Herring , Will Deacon Subject: [PATCH v4 1/2] PCI: pci-host-generic: add support for Synopsys DesignWare RC in ECAM mode Date: Fri, 6 Oct 2017 17:39:18 +0100 Message-Id: <20171006163919.14898-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171006163919.14898-1-ard.biesheuvel@linaro.org> References: <20171006163919.14898-1-ard.biesheuvel@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Some implementations of the Synopsys DesignWare PCIe controller implement a so-called ECAM shift mode, which allows a static memory window to be configured that covers the configuration space of the entire bus range. Usually, when the firmware performs all the low level configuration that is required to expose this controller in a fully ECAM compatible manner, we can simply describe it as "pci-host-ecam-generic" and be done with it. However, in some cases (e.g., the Marvell Armada 80x0 as well as the Socionext SynQuacer Soc), the IP was synthesized with an ATU window granularity that does not allow the first bus to be mapped in a way that prevents the device on the downstream port from appearing more than once, and so we still need special handling in software to drive this static almost-ECAM configuration. So extend the pci-host-generic driver so it can support these controllers as well, by adding special config space accessors that take the above quirk into account. Note that, unlike most drivers for this IP, this driver does not expose a fake bridge device at B/D/F 00:00.0. There is no point in doing so, given that this is not a true bridge, and does not require any windows to be configured in order for the downstream device to operate correctly. Omitting it also prevents the PCI resource allocation routines from handing out BAR space to it unnecessarily. Signed-off-by: Ard Biesheuvel Acked-by: Will Deacon --- drivers/pci/host/pci-host-generic.c | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/pci/host/pci-host-generic.c b/drivers/pci/host/pci-host-generic.c index 7d709a7e0aa8..01e81a30e303 100644 --- a/drivers/pci/host/pci-host-generic.c +++ b/drivers/pci/host/pci-host-generic.c @@ -35,6 +35,43 @@ static struct pci_ecam_ops gen_pci_cfg_cam_bus_ops = { } }; +static int pci_dw_ecam_config_read(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) +{ + struct pci_config_window *cfg = bus->sysdata; + + /* + * The Synopsys DesignWare PCIe controller in ECAM mode will not filter + * type 0 config TLPs sent to devices 1 and up on its downstream port, + * resulting in devices appearing multiple times on bus 0 unless we + * filter out those accesses here. + */ + if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + return pci_generic_config_read(bus, devfn, where, size, val); +} + +static int pci_dw_ecam_config_write(struct pci_bus *bus, u32 devfn, int where, + int size, u32 val) +{ + struct pci_config_window *cfg = bus->sysdata; + + if (bus->number == cfg->busr.start && PCI_SLOT(devfn) > 0) + return PCIBIOS_DEVICE_NOT_FOUND; + + return pci_generic_config_write(bus, devfn, where, size, val); +} + +static struct pci_ecam_ops pci_dw_ecam_bus_ops = { + .bus_shift = 20, + .pci_ops = { + .map_bus = pci_ecam_map_bus, + .read = pci_dw_ecam_config_read, + .write = pci_dw_ecam_config_write, + } +}; + static const struct of_device_id gen_pci_of_match[] = { { .compatible = "pci-host-cam-generic", .data = &gen_pci_cfg_cam_bus_ops }, @@ -42,6 +79,15 @@ static const struct of_device_id gen_pci_of_match[] = { { .compatible = "pci-host-ecam-generic", .data = &pci_generic_ecam_ops }, + { .compatible = "marvell,armada8k-pcie-ecam", + .data = &pci_dw_ecam_bus_ops }, + + { .compatible = "socionext,synquacer-pcie-ecam", + .data = &pci_dw_ecam_bus_ops }, + + { .compatible = "snps,dw-pcie-ecam", + .data = &pci_dw_ecam_bus_ops }, + { }, };