From patchwork Tue Sep 19 14:51:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Shishkin X-Patchwork-Id: 815562 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xxQnN4yW9z9s7m for ; Wed, 20 Sep 2017 00:51:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751586AbdISOvu (ORCPT ); Tue, 19 Sep 2017 10:51:50 -0400 Received: from mga04.intel.com ([192.55.52.120]:14165 "EHLO mga04.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750862AbdISOvu (ORCPT ); Tue, 19 Sep 2017 10:51:50 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Sep 2017 07:51:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,418,1500966000"; d="scan'208";a="1173787069" Received: from um.fi.intel.com (HELO localhost) ([10.237.72.212]) by orsmga001.jf.intel.com with ESMTP; 19 Sep 2017 07:51:47 -0700 From: Alexander Shishkin To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Shishkin , stable@vger.kernel.org Subject: [PATCH] PCI: Fixup the RTIT_BAR of Intel TH on Denverton Date: Tue, 19 Sep 2017 17:51:36 +0300 Message-Id: <20170919145136.13527-1-alexander.shishkin@linux.intel.com> X-Mailer: git-send-email 2.13.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On some intergrations of the Intel TH the reported size of RTIT_BAR doesn't match its actual size, which leads to overlaps with other devices' resources. For this reason, we need to resize the RTIT_BAR on Denverton where it would overlap with XHCI MMIO space. Signed-off-by: Alexander Shishkin Fixes: 5118ccd347 ("intel_th: pci: Add Denverton SOC support") Cc: stable@vger.kernel.org --- drivers/pci/quirks.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 6967c6b4cf..08a1e6629f 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4681,3 +4681,19 @@ static void quirk_intel_no_flr(struct pci_dev *dev) } DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr); + +static void quirk_intel_th_dnv(struct pci_dev *dev) +{ + struct resource *r = &dev->resource[4]; + + /* + * Denverton reports 2k of RTIT_BAR (intel_th resource 4), which + * appears to be 4 MB in reality. + */ + if (r->end == r->start + 0x7ff) { + r->start = 0; + r->end = 0x3fffff; + r->flags |= IORESOURCE_UNSET; + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_dnv);