From patchwork Wed Aug 30 14:24:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Glauber X-Patchwork-Id: 807657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3xj78N6nqKz9s7f for ; Thu, 31 Aug 2017 00:25:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751805AbdH3OZj (ORCPT ); Wed, 30 Aug 2017 10:25:39 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:34125 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751706AbdH3OZM (ORCPT ); Wed, 30 Aug 2017 10:25:12 -0400 Received: by mail-wm0-f68.google.com with SMTP id l19so1979867wmi.1; Wed, 30 Aug 2017 07:25:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6g0lkFSiY9+qwTZSmr4T+XOmcNxS9eDdmyr5PhhfFK0=; b=E5WNH+qjaFjqSlPz1Wg4t2wusFxiYHkuBCHDnuV2PBfkx30yFxnP6Ij0ibjq84RjkW CabwjmTVBrVZGxtkBOcZOowHMxAnybG0TvTPEJb1psw+bQJT5TtNbIUp2Ou+/EvBfZIx cayq+s/U3LW96n+WwvboI7op+T+zxGU2ucXX0wECM8OTrADfJLBTz7GfOFaPsGoy7bhU F+aCCF0FJiaHUTCP7cJHfkHjbPxsrpyf7afzDTRrZrxdUKMAtAGAdLrkUJvwqRa5OLEB agLU61OrKJVNmIBgFBwtSH72ZsvMMtpxMfs6qwJk4q0lgRCm8IHvP0/QQoIjxE+8ryNv SLng== X-Gm-Message-State: AHYfb5gyYDrycLOQ21eUDj+tfsjXtAJRREWnnttcn3Q7ytmrQYngSJm5 oWxke25Nmxky2EII X-Received: by 10.28.92.203 with SMTP id q194mr1636271wmb.165.1504103111476; Wed, 30 Aug 2017 07:25:11 -0700 (PDT) Received: from hc.fritz.box (HSI-KBW-46-223-66-184.hsi.kabel-badenwuerttemberg.de. [46.223.66.184]) by smtp.gmail.com with ESMTPSA id p105sm97012wrc.64.2017.08.30.07.25.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 30 Aug 2017 07:25:11 -0700 (PDT) From: Jan Glauber To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, Alex Williamson , linux-kernel@vger.kernel.org, david.daney@cavium.com, Jon Masters , Robert Richter , linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Jan Glauber Subject: [PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root ports Date: Wed, 30 Aug 2017 16:24:54 +0200 Message-Id: <20170830142454.10971-4-jglauber@cavium.com> X-Mailer: git-send-email 2.9.0.rc0.21.g7777322 In-Reply-To: <20170830142454.10971-1-jglauber@cavium.com> References: <20170830142454.10971-1-jglauber@cavium.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Root ports of cn8xxx do not function after a slot reset when used with some e1000e and LSI HBA devices. Add a quirk to prevent slot reset on these root ports. Signed-off-by: Jan Glauber --- drivers/pci/quirks.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 85191b8..6679971 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -845,6 +845,22 @@ static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); #endif +/* + * Root port on some Cavium CN8xxx chips do not successfully complete + * a bus reset when used with certain types of child devices. Config + * space access to the child may quit responding. Flag all devices under + * the secondary bus as non-resettable. + */ +static void quirk_CN8xxx_secondary_bus(struct pci_dev *dev) +{ + struct pci_dev *pdev; + + dev_warn(&dev->dev, "Cavium CN8xxx quirk detected; reset for devices on secondary bus disabled\n"); + list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) + pdev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_CN8xxx_secondary_bus); + /* * Some settings of MMRBC can lead to data corruption so block changes. * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide