From patchwork Wed Apr 5 08:52:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 747149 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vyfmv0RvTz9s85 for ; Wed, 5 Apr 2017 18:55:11 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="gbSbPyuo"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754823AbdDEIzG (ORCPT ); Wed, 5 Apr 2017 04:55:06 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:50073 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754528AbdDEIy2 (ORCPT ); Wed, 5 Apr 2017 04:54:28 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v358rwvT011347; Wed, 5 Apr 2017 03:53:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1491382438; bh=qJmZ/UKOX92O/fLom1JFGSGnKzBEyF8sfsPsotKZMfk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gbSbPyuoCHFJbk0S2Ktgt3QsmYA/AdqbjQWn78HW23m7/2u4y8knnPiDw0jgaFm2I maxho1d4U/H34FJzX/P9+LrBlOrRVCS2eVVxI4OGOdGITUGFx0SSHCVSVu6Jrew37R LuHyofeEwbZrels8n82alPQxAlZ634qAvVtQh7wQ= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v358rw2C028553; Wed, 5 Apr 2017 03:53:58 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 5 Apr 2017 03:53:57 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v358qrhs012909; Wed, 5 Apr 2017 03:53:54 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , , Subject: [PATCH v6 15/23] dt-bindings: PCI: dra7xx: Add DT bindings to enable unaligned access Date: Wed, 5 Apr 2017 14:22:35 +0530 Message-ID: <20170405085243.18123-16-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170405085243.18123-1-kishon@ti.com> References: <20170405085243.18123-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update device tree binding documentation of TI's dra7xx PCI controller to include property for enabling unaligned mem access. Signed-off-by: Kishon Vijay Abraham I Acked-by: Rob Herring Signed-off-by: Bjorn Helgaas --- Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt index 60c3cccefabc..6a07c96227e0 100644 --- a/Documentation/devicetree/bindings/pci/ti-pci.txt +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt @@ -39,6 +39,11 @@ DEVICE MODE - interrupts : one interrupt entries must be specified for main interrupt. - num-ib-windows : number of inbound address translation windows - num-ob-windows : number of outbound address translation windows + - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument + should contain the register offset within syscon + and the 2nd argument should contain the bit field + for setting the bit to enable unaligned + access. Optional Property: - gpios : Should be added if a gpio line is required to drive PERST# line