From patchwork Thu Sep 1 16:44:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 664969 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sQ7Qr2p0sz9sRZ for ; Fri, 2 Sep 2016 02:45:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934836AbcIAQoe (ORCPT ); Thu, 1 Sep 2016 12:44:34 -0400 Received: from mail.kernel.org ([198.145.29.136]:56636 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934707AbcIAQob (ORCPT ); Thu, 1 Sep 2016 12:44:31 -0400 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D1FB520376; Thu, 1 Sep 2016 16:44:29 +0000 (UTC) Received: from localhost (unknown [69.71.1.1]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 66E0A2037C; Thu, 1 Sep 2016 16:44:28 +0000 (UTC) Subject: [PATCH 4/9] Rename struct rockchip_pcie_port to struct rockchip_pcie. To: Shawn Lin From: Bjorn Helgaas Cc: devicetree@vger.kernel.org, Wenrui Li , Heiko Stuebner , Arnd Bergmann , Marc Zyngier , linux-pci@vger.kernel.org, Brian Norris , linux-kernel@vger.kernel.org, Doug Anderson , linux-rockchip@lists.infradead.org, Rob Herring , Guenter Roeck Date: Thu, 01 Sep 2016 11:44:26 -0500 Message-ID: <20160901164426.14195.70566.stgit@bhelgaas-glaptop2.roam.corp.google.com> In-Reply-To: <20160901163758.14195.15725.stgit@bhelgaas-glaptop2.roam.corp.google.com> References: <20160901163758.14195.15725.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, NML_ADSP_CUSTOM_MED,UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org --- drivers/pci/host/pcie-rockchip.c | 46 +++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 23 deletions(-) --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 3cfb47a..63fb0ebc 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -178,7 +178,7 @@ PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \ PCIE_CLIENT_INT_PHY) -struct rockchip_pcie_port { +struct rockchip_pcie { void __iomem *reg_base; /* DT axi-base */ void __iomem *apb_base; /* DT apb-base */ struct phy *phy; @@ -200,17 +200,17 @@ struct rockchip_pcie_port { struct irq_domain *irq_domain; }; -static u32 rockchip_pcie_read(struct rockchip_pcie_port *rockchip, u32 reg) +static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg) { return readl(rockchip->apb_base + reg); } -static void rockchip_pcie_write(struct rockchip_pcie_port *rockchip, u32 val, u32 reg) +static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val, u32 reg) { writel(val, rockchip->apb_base + reg); } -static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *rockchip) +static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip) { u32 status; @@ -219,7 +219,7 @@ static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *rockchip) rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR); } -static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *rockchip) +static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) { u32 status; @@ -228,7 +228,7 @@ static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *rockchip) rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR); } -static int rockchip_pcie_valid_device(struct rockchip_pcie_port *rockchip, +static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip, struct pci_bus *bus, int dev) { /* access only one slot on each root port */ @@ -245,7 +245,7 @@ static int rockchip_pcie_valid_device(struct rockchip_pcie_port *rockchip, return 1; } -static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *rockchip, +static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip, int where, int size, u32 *val) { void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where; @@ -268,7 +268,7 @@ static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *rockchip, return PCIBIOS_SUCCESSFUL; } -static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *rockchip, +static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip, int where, int size, u32 val) { u32 mask, tmp, offset; @@ -289,7 +289,7 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *rockchip, return PCIBIOS_SUCCESSFUL; } -static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *rockchip, +static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { @@ -316,7 +316,7 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *rockchip, return PCIBIOS_SUCCESSFUL; } -static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *rockchip, +static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip, struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { @@ -342,7 +342,7 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *rockchip, static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - struct rockchip_pcie_port *rockchip = bus->sysdata; + struct rockchip_pcie *rockchip = bus->sysdata; if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) { *val = 0xffffffff; @@ -358,7 +358,7 @@ static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - struct rockchip_pcie_port *rockchip = bus->sysdata; + struct rockchip_pcie *rockchip = bus->sysdata; if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) return PCIBIOS_DEVICE_NOT_FOUND; @@ -378,7 +378,7 @@ static struct pci_ops rockchip_pcie_ops = { * rockchip_pcie_init_port - Initialize hardware * @rockchip: PCIe port information */ -static int rockchip_pcie_init_port(struct rockchip_pcie_port *rockchip) +static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) { int err; u32 status; @@ -579,7 +579,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie_port *rockchip) static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg) { - struct rockchip_pcie_port *rockchip = arg; + struct rockchip_pcie *rockchip = arg; u32 reg; u32 sub_reg; @@ -642,7 +642,7 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg) static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg) { - struct rockchip_pcie_port *rockchip = arg; + struct rockchip_pcie *rockchip = arg; u32 reg; reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS); @@ -684,7 +684,7 @@ static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg) static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); - struct rockchip_pcie_port *rockchip; + struct rockchip_pcie *rockchip; u32 reg; u32 hwirq; u32 virq; @@ -717,7 +717,7 @@ static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc) * * Return: '0' on success and error value on failure */ -static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *rockchip) +static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->dev; struct platform_device *pdev = to_platform_device(dev); @@ -874,7 +874,7 @@ static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *rockchip) return 0; } -static int rockchip_pcie_set_vpcie(struct rockchip_pcie_port *rockchip) +static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip) { int err; @@ -914,7 +914,7 @@ err_out: return err; } -static void rockchip_pcie_enable_interrupts(struct rockchip_pcie_port *rockchip) +static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip) { rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) & (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK); @@ -936,7 +936,7 @@ static const struct irq_domain_ops intx_domain_ops = { .map = rockchip_pcie_intx_map, }; -static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *rockchip) +static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->dev; struct device_node *intc = of_get_next_child(dev->of_node, NULL); @@ -956,7 +956,7 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *rockchip) return 0; } -static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *rockchip, +static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip, int region_no, int type, u8 num_pass_bits, u32 lower_addr, u32 upper_addr) { @@ -996,7 +996,7 @@ static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *rockchip, return 0; } -static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *rockchip, +static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip, int region_no, u8 num_pass_bits, u32 lower_addr, u32 upper_addr) { @@ -1026,7 +1026,7 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *rockchip, static int rockchip_pcie_probe(struct platform_device *pdev) { - struct rockchip_pcie_port *rockchip; + struct rockchip_pcie *rockchip; struct device *dev = &pdev->dev; struct pci_bus *bus, *child; struct resource_entry *win;