From patchwork Thu Dec 10 19:50:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 555315 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id F10DD140BEC for ; Fri, 11 Dec 2015 06:50:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751449AbbLJTuG (ORCPT ); Thu, 10 Dec 2015 14:50:06 -0500 Received: from mail.kernel.org ([198.145.29.136]:47566 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750962AbbLJTuE (ORCPT ); Thu, 10 Dec 2015 14:50:04 -0500 Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E464B205CA; Thu, 10 Dec 2015 19:50:03 +0000 (UTC) Received: from localhost (unknown [69.71.1.1]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 039D120434; Thu, 10 Dec 2015 19:50:02 +0000 (UTC) Subject: [PATCH] lspci: Decode DevCap SlotPowerLimit for all components with Upstream Ports To: Martin Mares From: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Date: Thu, 10 Dec 2015 13:50:01 -0600 Message-ID: <20151210195001.8111.55134.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, NML_ADSP_CUSTOM_MED,UNPARSEABLE_RELAY autolearn=no version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The SlotPowerLimit in the Slot Capability indicates how much power the slot can supply to a downstream device. A Root Port or Switch Downstream Port communicates the limit via a Set_Slot_Power_Limit Message on the link. The component on the other end of the link copies the limit from the message to the Captured Slot Power Limit in its Device Capability [see PCIe r3.0, sec 2.2.8.5]. The Captured SlotPowerLimit is relevant for all devices on the downstream end of a Link. This includes Endpoints and Bridges as well as Switch Upstream Ports. Decode the DevCap Captured SlotPowerLimit for Endpoints and Bridges as well as Switch Upstream Ports. Signed-off-by: Bjorn Helgaas --- ls-caps.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/ls-caps.c b/ls-caps.c index c145ed6..639f931 100644 --- a/ls-caps.c +++ b/ls-caps.c @@ -678,7 +678,8 @@ static void cap_express_dev(struct device *d, int where, int type) if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END)) printf(" FLReset%c", FLAG(t, PCI_EXP_DEVCAP_FLRESET)); - if (type == PCI_EXP_TYPE_UPSTREAM) + if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) || + (type == PCI_EXP_TYPE_PCI_BRIDGE)) printf(" SlotPowerLimit %.3fW", power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18, (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));