From patchwork Tue Feb 24 08:35:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 442851 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id AD587140159 for ; Tue, 24 Feb 2015 19:35:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751856AbbBXIfJ (ORCPT ); Tue, 24 Feb 2015 03:35:09 -0500 Received: from mail-pa0-f48.google.com ([209.85.220.48]:40952 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751225AbbBXIfH (ORCPT ); Tue, 24 Feb 2015 03:35:07 -0500 Received: by paceu11 with SMTP id eu11so34398740pac.7 for ; Tue, 24 Feb 2015 00:35:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=Pa5tgkVu3CssC6PMVNJj5y80S0udrin/wqXQFc6j4fU=; b=WCzigCnOVFtBDqgf0aIBYlQ6/HHeyvdrnjYIkM7CXUzEySV2egZH/6M/Ujc23rMmi/ h4wOuDFe7u3eLB7UuSSjI5fm+IyK+B77QdnogYXDSeLgYqo5lN9+l48Tapqyxhh6w0Vd xDl0zcdx+5rmuK3xxCWpVf6dFh6TbgLH/2dGjEYw8Qq8msf1IPIaJSDifoUS8ZJ9XY8j 5srjh4r4N4EloDpXxcI09LzLKc2jFh6sg/cAfhNtH79hzmVAZ847syj1Afif4ssEPQWP vtBhZbtiGbH70EsDCHjO9LYM/d2jM9kge//HXU/O4P8gl1SZjUKChVmj/xb+ZXim9tIW O9aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:subject:to:from:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-type :content-transfer-encoding; bh=Pa5tgkVu3CssC6PMVNJj5y80S0udrin/wqXQFc6j4fU=; b=FP2KYuM3Ef/gjndt5lqI8YLC67MBXow57uBIs7Ue3Vc1NJ8QLXm/8IegEVEnEauacy 3gcxpm3sILpxHkxFU7IDBo8uEdfveyAGqqWDdqAji9jM5mSOHu0SQWn0hRTg01UrzhWa VSeZoQOQ7qE9VHe3mXv1N84jQKH8xkdXvLt+1kAlCKmibnj60HxakthyzuqLOwydF6Vw KemwkuITiirgHa3kEPEWEaN/F2sENM8cuKJWtyoEqnkQ1OSE1DjbyNtFuDhsqSqPT8ZM H5f+H1mb1LSfNw922J27Gh1in8x+RIR21ahNROHhhgoIQRWRRKId43ifpuO8qwd60OmO 3Ycw== X-Gm-Message-State: ALoCoQm1+fTZsnWWQtstq7bzOuIhuXaqo78MQ9b4uwrck856tTDYqeHKvRxzXUouN6h8jU1cR0n5 X-Received: by 10.70.133.130 with SMTP id pc2mr26298532pdb.99.1424766907386; Tue, 24 Feb 2015 00:35:07 -0800 (PST) Received: from localhost ([12.23.74.29]) by mx.google.com with ESMTPSA id ez1sm38246524pdb.22.2015.02.24.00.35.06 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 24 Feb 2015 00:35:06 -0800 (PST) Subject: [PATCH v12 18/21] powerpc/powernv: Reserve additional space for IOV BAR, with m64_per_iov supported To: Wei Yang , benh@au1.ibm.com, gwshan@linux.vnet.ibm.com From: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Date: Tue, 24 Feb 2015 02:35:04 -0600 Message-ID: <20150224083504.32124.23374.stgit@bhelgaas-glaptop2.roam.corp.google.com> In-Reply-To: <20150224082939.32124.45744.stgit@bhelgaas-glaptop2.roam.corp.google.com> References: <20150224082939.32124.45744.stgit@bhelgaas-glaptop2.roam.corp.google.com> User-Agent: StGit/0.16 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Wei Yang M64 aperture size is limited on PHB3. When the IOV BAR is too big, this will exceed the limitation and failed to be assigned. Introduce a different mechanism based on the IOV BAR size: - if IOV BAR size is smaller than 64MB, expand to total_pe - if IOV BAR size is bigger than 64MB, roundup power2 [bhelgaas: make dev_printk() output more consistent, use PCI_SRIOV_NUM_BARS] Signed-off-by: Wei Yang Signed-off-by: Bjorn Helgaas --- arch/powerpc/include/asm/pci-bridge.h | 2 ++ arch/powerpc/platforms/powernv/pci-ioda.c | 33 ++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h index 011340df8583..d824bb184ab8 100644 --- a/arch/powerpc/include/asm/pci-bridge.h +++ b/arch/powerpc/include/asm/pci-bridge.h @@ -179,6 +179,8 @@ struct pci_dn { u16 max_vfs; /* number of VFs IOV BAR expended */ u16 vf_pes; /* VF PE# under this PF */ int offset; /* PE# for the first VF PE */ +#define M64_PER_IOV 4 + int m64_per_iov; #define IODA_INVALID_M64 (-1) int m64_wins[PCI_SRIOV_NUM_BARS]; #endif /* CONFIG_PCI_IOV */ diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index a3c2fbe35fc8..30b7c3909746 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -2242,6 +2242,7 @@ static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) int i; resource_size_t size; struct pci_dn *pdn; + int mul, total_vfs; if (!pdev->is_physfn || pdev->is_added) return; @@ -2252,6 +2253,32 @@ static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) pdn = pci_get_pdn(pdev); pdn->max_vfs = 0; + total_vfs = pci_sriov_get_totalvfs(pdev); + pdn->m64_per_iov = 1; + mul = phb->ioda.total_pe; + + for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { + res = &pdev->resource[i + PCI_IOV_RESOURCES]; + if (!res->flags || res->parent) + continue; + if (!pnv_pci_is_mem_pref_64(res->flags)) { + dev_warn(&pdev->dev, " non M64 VF BAR%d: %pR\n", + i, res); + continue; + } + + size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); + + /* bigger than 64M */ + if (size > (1 << 26)) { + dev_info(&pdev->dev, "PowerNV: VF BAR%d: %pR IOV size is bigger than 64M, roundup power2\n", + i, res); + pdn->m64_per_iov = M64_PER_IOV; + mul = __roundup_pow_of_two(total_vfs); + break; + } + } + for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { res = &pdev->resource[i + PCI_IOV_RESOURCES]; if (!res->flags || res->parent) @@ -2264,12 +2291,12 @@ static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); - res->end = res->start + size * phb->ioda.total_pe - 1; + res->end = res->start + size * mul - 1; dev_dbg(&pdev->dev, " %pR\n", res); dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", - i, res, phb->ioda.total_pe); + i, res, mul); } - pdn->max_vfs = phb->ioda.total_pe; + pdn->max_vfs = mul; } static void pnv_pci_ioda_fixup_sriov(struct pci_bus *bus)