From patchwork Fri Nov 1 16:56:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 287874 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 601482C00A1 for ; Sat, 2 Nov 2013 04:11:44 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753337Ab3KARLn (ORCPT ); Fri, 1 Nov 2013 13:11:43 -0400 Received: from quartz.orcorp.ca ([184.70.90.242]:39548 "EHLO quartz.orcorp.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753107Ab3KARLm (ORCPT ); Fri, 1 Nov 2013 13:11:42 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=obsidianresearch.com; s=rsa1; h=In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date; bh=EI0LkAXiX3DJEjWszyHrtruVDAoijiau2729bpQZwPA=; b=Ix1hDm7S5xqtQuY32AAquojJKlfecPIWtb8S2Q27LDNIxQEKhY/YgetIOvdga4e9xOm2qP4GQFxUC5LsUhUzdccxCv8aUdZFM8mgc5AC+qRVsIAc5n6W0AQUdeVD32JM6a4LlqwDVz2JasbxxskRbwMBceivSzIUdEoG/MrMV9Q=; Received: from [10.0.0.161] (helo=jggl.edm.orcorp.ca) by quartz.orcorp.ca with esmtps (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1VcI13-0003VF-Ok; Fri, 01 Nov 2013 10:56:09 -0600 Received: from jgg by jggl.edm.orcorp.ca with local (Exim 4.80) (envelope-from ) id 1VcI13-0008Rd-Cm; Fri, 01 Nov 2013 10:56:09 -0600 Date: Fri, 1 Nov 2013 10:56:09 -0600 From: Jason Gunthorpe To: Bjorn Helgaas Cc: Thomas Petazzoni , Jason Cooper , Ezequiel Garcia , linux-arm , "linux-pci@vger.kernel.org" Subject: Re: [PATCH v2] PCI: mvebu - Support a bridge with no IO port window Message-ID: <20131101165609.GA25978@obsidianresearch.com> References: <1381868182-8544-1-git-send-email-jgunthorpe@obsidianresearch.com> <20131031101357.5a56e2d0@skate> <20131031164810.GA26426@obsidianresearch.com> <20131031233245.GA9853@obsidianresearch.com> <20131101052848.GA20163@obsidianresearch.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Broken-Reverse-DNS: no host name found for IP address 10.0.0.161 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org > I don't know why 0xf0f0. Anything that's non-zero in the upper four > bits of each byte should work to determine writability. It seems like > it would be safer to write 0x00f0 so the window is disabled, because > even if we're enumerating the bridge at hot-plug time, nobody else > should be trying to access a device behind the bridge, and we wouldn't > inadvertently claim something destined for [io 0xf000-0xffff]. What do you think of this? From f1f0d6a5b192a46585c5fefdc7ec06808639be4d Mon Sep 17 00:00:00 2001 From: Jason Gunthorpe Date: Fri, 1 Nov 2013 10:54:13 -0600 Subject: [PATCH] PCI: Use a safer method to determine if a bridge has IO support We want to avoid disturbing an active an enabled bus during IO detection, so first check if IO is enabled - if so then we know for sure that the bridge has IO. Otherwise we can safely fiddle with the IO window register to detect IO, as IO is disabled. This also changes the probe value to 0x00f0, which is intended to be clearer to the reader that this is just a probe. Signed-off-by: Jason Gunthorpe --- drivers/pci/setup-bus.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index bc26d79..d63087f 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -665,10 +665,16 @@ static void pci_bridge_check_ranges(struct pci_bus *bus) pci_read_config_word(bridge, PCI_IO_BASE, &io); if (!io) { - pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); - pci_read_config_word(bridge, PCI_IO_BASE, &io); - pci_write_config_word(bridge, PCI_IO_BASE, 0x0); - } + u16 command; + pci_read_config_word(bridge, PCI_COMMAND, &command); + if (command & PCI_COMMAND_IO) + b_res[0].flags |= IORESOURCE_IO; + else { + pci_write_config_word(bridge, PCI_IO_BASE, 0x00f0); + pci_read_config_word(bridge, PCI_IO_BASE, &io); + pci_write_config_word(bridge, PCI_IO_BASE, 0x0); + } + } if (io) b_res[0].flags |= IORESOURCE_IO; /* DECchip 21050 pass 2 errata: the bridge may miss an address