From patchwork Fri Sep 6 17:13:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 273282 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 200EF2C007E for ; Sat, 7 Sep 2013 03:13:37 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752991Ab3IFRNg (ORCPT ); Fri, 6 Sep 2013 13:13:36 -0400 Received: from mail-yh0-f45.google.com ([209.85.213.45]:46357 "EHLO mail-yh0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752963Ab3IFRNf (ORCPT ); Fri, 6 Sep 2013 13:13:35 -0400 Received: by mail-yh0-f45.google.com with SMTP id i7so1006398yha.4 for ; Fri, 06 Sep 2013 10:13:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=6LM1i51jMZeJ07uDGt5mM77y/OQGEZzrRbO8m8r1/SI=; b=TIAxTaXSF4ADpdSS46xTFQqIlojgybna43zMOGfBDyckpwz7bo4VB9nJ5FILcG1O// fyHZgNAm741jHgkT/PMUPqhKoE/HiQCMEk9P3D/kZUM7pPn3bwWLY6PuL2XLoOkWzZn5 0xb3Q4rO/XYrm0rEWuun026YS11qEzugfKxxOIvs/GqUYLLijXmbc83elZPExL/El59s 7zJ4RbvjRLvyfz50PwboAk9s5a40k2Aj+oKYc3QmvyAqPquUUah3Y17biYN3pwIJ8Bml 3u8tUN+Oud5AZN+a0tyYvj3uRGBoTOm/1CQ1vk58U+TZczm4Ugw5sFREXpDZlyddUksC dpsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:subject:to:from:cc:date:message-id:in-reply-to :references:user-agent:mime-version:content-type :content-transfer-encoding; bh=6LM1i51jMZeJ07uDGt5mM77y/OQGEZzrRbO8m8r1/SI=; b=eSUkFfrzmsrcyetRQnasX+hCdKXZisWvBrdcIEcip4abltJAmtzqZKsjw/WpDB2yp6 b8FseDAMqZdU03YWJ+8aQe3J9TN+ddSTFV4Wyzh++Fai5MkZJ1l8l4cAjwAf9M0YKAci RUv6I6qL2i5vBoiJiOJ2zkU13qEmCcXq+EEt5I7ZPvnBNXvJIXoJLtndyNuKA9e5jcih Cq6dr4nbnRX2JxRReT4tum4MtrjTrADqfKdGbSsCqZ25YZA6JjTET8mTt5PQLq9CatN4 9XWHkzV1pLAY6aKQ2IJj2bFD1ibOQH8YPhekdPKkAcCDiz2kTtA4Qe0Z3J6QSnMuK3da qEtw== X-Gm-Message-State: ALoCoQlvi8gyLVdFUTAMZACpFYeMfvTyZ6FjFaC94agQAHNy8rr1Usz9Zsd+v1Qz8xgp6NHYfW4OQCXWFCfUJvBEaI7HHawu4k2rW8hOsMo61ib9njXDZ1yoBgs1RyXkYOL9bEd/nPaW/6wJGitXfrP5/h+HLwFABG3f0RyrgdV6fK2eVzsxQaS76AqHBTPTNTmMTfF4/NmCvQlpGZTHOy+vxSc11K+hBSNx43YnlLAAnB1nEzrGx2Q= X-Received: by 10.236.14.71 with SMTP id c47mr35844yhc.132.1378487615133; Fri, 06 Sep 2013 10:13:35 -0700 (PDT) Received: from localhost ([172.16.53.165]) by mx.google.com with ESMTPSA id g47sm4037803yhb.21.1969.12.31.16.00.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 06 Sep 2013 10:13:34 -0700 (PDT) Subject: [PATCH 01/14] ACPI: Write _OSC bit field definitions in hex To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: "Rafael J. Wysocki" , linux-acpi@vger.kernel.org, Len Brown Date: Fri, 06 Sep 2013 11:13:32 -0600 Message-ID: <20130906171332.11482.45745.stgit@bhelgaas-glaptop> In-Reply-To: <20130906171010.11482.34235.stgit@bhelgaas-glaptop> References: <20130906171010.11482.34235.stgit@bhelgaas-glaptop> User-Agent: StGit/0.16 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Update _OSC definition comments to correspond to the 1-based spec wording (DWORD 1, etc.) Write _OSC field #defines as hex to make clear that they are bits in a 32-bit DWORD, not arbitrary values. No functional change. Signed-off-by: Bjorn Helgaas --- include/linux/acpi.h | 54 +++++++++++++++++++++++++------------------------- 1 file changed, 27 insertions(+), 27 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/include/linux/acpi.h b/include/linux/acpi.h index a5db4ae..285de6f 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -304,39 +304,39 @@ struct acpi_osc_context { #define OSC_SUPPORT_TYPE 1 #define OSC_CONTROL_TYPE 2 -/* _OSC DW0 Definition */ -#define OSC_QUERY_ENABLE 1 -#define OSC_REQUEST_ERROR 2 -#define OSC_INVALID_UUID_ERROR 4 -#define OSC_INVALID_REVISION_ERROR 8 -#define OSC_CAPABILITIES_MASK_ERROR 16 +/* _OSC Capabilities DWORD 1: Query/Control and Error Returns (generic) */ +#define OSC_QUERY_ENABLE 0x00000001 /* input */ +#define OSC_REQUEST_ERROR 0x00000002 /* return */ +#define OSC_INVALID_UUID_ERROR 0x00000004 /* return */ +#define OSC_INVALID_REVISION_ERROR 0x00000008 /* return */ +#define OSC_CAPABILITIES_MASK_ERROR 0x00000010 /* return */ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context); -/* platform-wide _OSC bits */ -#define OSC_SB_PAD_SUPPORT 1 -#define OSC_SB_PPC_OST_SUPPORT 2 -#define OSC_SB_PR3_SUPPORT 4 -#define OSC_SB_HOTPLUG_OST_SUPPORT 8 -#define OSC_SB_APEI_SUPPORT 16 +/* Platform-Wide Capabilities _OSC: Capabilities DWORD 2: Support Field */ +#define OSC_SB_PAD_SUPPORT 0x00000001 +#define OSC_SB_PPC_OST_SUPPORT 0x00000002 +#define OSC_SB_PR3_SUPPORT 0x00000004 +#define OSC_SB_HOTPLUG_OST_SUPPORT 0x00000008 +#define OSC_SB_APEI_SUPPORT 0x00000010 +#define OSC_SB_CPC_SUPPORT 0x00000020 extern bool osc_sb_apei_support_acked; -/* PCI defined _OSC bits */ -/* _OSC DW1 Definition (OS Support Fields) */ -#define OSC_EXT_PCI_CONFIG_SUPPORT 1 -#define OSC_ACTIVE_STATE_PWR_SUPPORT 2 -#define OSC_CLOCK_PWR_CAPABILITY_SUPPORT 4 -#define OSC_PCI_SEGMENT_GROUPS_SUPPORT 8 -#define OSC_MSI_SUPPORT 16 -#define OSC_PCI_SUPPORT_MASKS 0x1f - -/* _OSC DW1 Definition (OS Control Fields) */ -#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL 1 -#define OSC_SHPC_NATIVE_HP_CONTROL 2 -#define OSC_PCI_EXPRESS_PME_CONTROL 4 -#define OSC_PCI_EXPRESS_AER_CONTROL 8 -#define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL 16 +/* PCI Host Bridge _OSC: Capabilities DWORD 2: Support Field */ +#define OSC_EXT_PCI_CONFIG_SUPPORT 0x00000001 +#define OSC_ACTIVE_STATE_PWR_SUPPORT 0x00000002 +#define OSC_CLOCK_PWR_CAPABILITY_SUPPORT 0x00000004 +#define OSC_PCI_SEGMENT_GROUPS_SUPPORT 0x00000008 +#define OSC_MSI_SUPPORT 0x00000010 +#define OSC_PCI_SUPPORT_MASKS 0x0000001f + +/* PCI Host Bridge _OSC: Capabilities DWORD 3: Control Field */ +#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL 0x00000001 +#define OSC_SHPC_NATIVE_HP_CONTROL 0x00000002 +#define OSC_PCI_EXPRESS_PME_CONTROL 0x00000004 +#define OSC_PCI_EXPRESS_AER_CONTROL 0x00000008 +#define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL 0x00000010 #define OSC_PCI_CONTROL_MASKS (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL | \ OSC_SHPC_NATIVE_HP_CONTROL | \