From patchwork Mon Jul 9 20:32:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 169952 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id DE9DE2C00DC for ; Tue, 10 Jul 2012 06:32:39 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753315Ab2GIUcU (ORCPT ); Mon, 9 Jul 2012 16:32:20 -0400 Received: from mail-fa0-f74.google.com ([209.85.161.74]:46745 "EHLO mail-fa0-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753311Ab2GIUcQ (ORCPT ); Mon, 9 Jul 2012 16:32:16 -0400 Received: by mail-fa0-f74.google.com with SMTP id 25so573213fat.1 for ; Mon, 09 Jul 2012 13:32:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding; bh=WuJJRuPeS91yCxIuBqAEbjndclbt9JEtv8wZoXOCrE0=; b=oz2KqeTYC/5kE8Q7+RdE/QSublD1xYtEvHajnx2nSUS1ouIkX1R6fy/gpoubgUHsFi 6GdLX41YH2KrOtpvAR+ZXVPsDRSLggJ981f+dB+NOl3tF1oAZZ6jmwz2Uwg0/zFFBy6s QtI8bTSFcidnjvrZDhKtnTEuLPTpdySb3ti/5s5yZV8u2sN0Y6lLHvwDfe23r1oXWyos FiQNXgBfoCfy94UhAiQEEUM2ZdXRGjfNHhuTi4XfjrjKYnsOFlMiYDornnq8NHN2Rz6K DOoB/XGOjmk0A3KJ18oCfPWPUrBshkGCE8MjNfJc6QNpddyHZxCXx/T4w0BRxVKiQNTx ig+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=subject:to:from:cc:date:message-id:in-reply-to:references :user-agent:mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=WuJJRuPeS91yCxIuBqAEbjndclbt9JEtv8wZoXOCrE0=; b=OInSJjAWoe8tZXiFplnwSE1sok2Hlk4rTFCCJMk4FQFjaet0Oa6PbofT+3PZGyX3I8 gwicU8WBqwAmb/CE/y4vt66rO6fFzlUgy4tsj/E/CCDtssygKe9nwq5gQlaMmEIW40xJ BoTbpeIzMOBuBV5oSN0AX+CL/10YpnWTniT4vdgs0BnchcVpmljj7vnArFX4dgE1wehL jdx+QnhFr52HVvcL3HdthoTVLdDuwnVLMRRmre+Viag/Us0HG9XCQNCtPH/J7CsDNwNp WfbUDFlnjwpnh2y5zApIE7ApPm3oS0D6AN9bJX2yyReNguwFovoJfziYYgDsYTEsxroA SUSQ== Received: by 10.14.187.140 with SMTP id y12mr13315435eem.9.1341865935454; Mon, 09 Jul 2012 13:32:15 -0700 (PDT) Received: by 10.14.187.140 with SMTP id y12mr13315422eem.9.1341865935285; Mon, 09 Jul 2012 13:32:15 -0700 (PDT) Received: from hpza10.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id d52si23179126eei.1.2012.07.09.13.32.15 (version=TLSv1/SSLv3 cipher=AES128-SHA); Mon, 09 Jul 2012 13:32:15 -0700 (PDT) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.18.96.155]) by hpza10.eem.corp.google.com (Postfix) with ESMTP id D571820004E; Mon, 9 Jul 2012 13:32:14 -0700 (PDT) Received: from bhelgaas.mtv.corp.google.com (unknown [IPv6:::1]) by bhelgaas.mtv.corp.google.com (Postfix) with ESMTP id 3DF901806EA; Mon, 9 Jul 2012 13:32:14 -0700 (PDT) Subject: [PATCH 3/3] sparc/PCI: replace pci_cfg_fake_ranges() with pci_read_bridge_bases() To: linux-pci@vger.kernel.org From: Bjorn Helgaas Cc: sparclinux@vger.kernel.org, Daniel Yeisley , Yinghai Lu , linux-kernel@vger.kernel.org, "David S. Miller" Date: Mon, 09 Jul 2012 14:32:14 -0600 Message-ID: <20120709203214.28178.71922.stgit@bhelgaas.mtv.corp.google.com> In-Reply-To: <20120709202308.28178.58942.stgit@bhelgaas.mtv.corp.google.com> References: <20120709202308.28178.58942.stgit@bhelgaas.mtv.corp.google.com> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlPOH2k9LLxMKeQ7oWZtKWF5mqDoLhK9lgcqVdAtVVf1mNsF191FAIB3CVqlTita3uY5dnzY78Wq83x3t/Xl+00nYJsSxRp1eaDH/wIPwDDPTk+WD3fDrxHdct4vlETdLrpDeWZrtZdPyOMhquTxSHhuFLDN3RHphBYkznnKFIIuAtBvmXwJ78Qbv0IFL5eaQhWMfCl Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The generic code to read P2P bridge windows is functionally equivalent to the sparc-specific pci_cfg_fake_ranges(), so use the generic code. The "if (!res->start) res->start = ..." removed from the I/O window code here was an artifact of the Intel 1K window support from 9d265124d051 and is no longer necessary (it probably was just cloned from x86 and was never useful on sparc). CC: "David S. Miller" CC: sparclinux@vger.kernel.org Signed-off-by: Bjorn Helgaas Acked-by: David S. Miller --- arch/sparc/kernel/pci.c | 89 +---------------------------------------------- 1 files changed, 1 insertions(+), 88 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c index fdaf218..fa53d55 100644 --- a/arch/sparc/kernel/pci.c +++ b/arch/sparc/kernel/pci.c @@ -375,93 +375,6 @@ static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) *last_p = last; } -/* For PCI bus devices which lack a 'ranges' property we interrogate - * the config space values to set the resources, just like the generic - * Linux PCI probing code does. - */ -static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev, - struct pci_bus *bus, - struct pci_pbm_info *pbm) -{ - struct pci_bus_region region; - struct resource *res, res2; - u8 io_base_lo, io_limit_lo; - u16 mem_base_lo, mem_limit_lo; - unsigned long base, limit; - - pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); - pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); - base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; - limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; - - if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { - u16 io_base_hi, io_limit_hi; - - pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); - pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); - base |= (io_base_hi << 16); - limit |= (io_limit_hi << 16); - } - - res = bus->resource[0]; - if (base <= limit) { - res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; - res2.flags = res->flags; - region.start = base; - region.end = limit + 0xfff; - pcibios_bus_to_resource(dev, &res2, ®ion); - if (!res->start) - res->start = res2.start; - if (!res->end) - res->end = res2.end; - } - - pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); - pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); - base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; - limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; - - res = bus->resource[1]; - if (base <= limit) { - res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | - IORESOURCE_MEM); - region.start = base; - region.end = limit + 0xfffff; - pcibios_bus_to_resource(dev, res, ®ion); - } - - pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); - pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); - base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; - limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; - - if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { - u32 mem_base_hi, mem_limit_hi; - - pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); - pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); - - /* - * Some bridges set the base > limit by default, and some - * (broken) BIOSes do not initialize them. If we find - * this, just assume they are not being used. - */ - if (mem_base_hi <= mem_limit_hi) { - base |= ((long) mem_base_hi) << 32; - limit |= ((long) mem_limit_hi) << 32; - } - } - - res = bus->resource[2]; - if (base <= limit) { - res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | - IORESOURCE_MEM | IORESOURCE_PREFETCH); - region.start = base; - region.end = limit + 0xfffff; - pcibios_bus_to_resource(dev, res, ®ion); - } -} - /* Cook up fake bus resources for SUNW,simba PCI bridges which lack * a proper 'ranges' property. */ @@ -550,7 +463,7 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, apb_fake_ranges(dev, bus, pbm); goto after_ranges; } else if (ranges == NULL) { - pci_cfg_fake_ranges(dev, bus, pbm); + pci_read_bridge_bases(bus); goto after_ranges; } i = 1;