From patchwork Fri Apr 27 17:41:41 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Helgaas X-Patchwork-Id: 155557 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5DD96B6FBB for ; Sat, 28 Apr 2012 03:41:44 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760583Ab2D0Rln (ORCPT ); Fri, 27 Apr 2012 13:41:43 -0400 Received: from mail-qa0-f74.google.com ([209.85.216.74]:43013 "EHLO mail-qa0-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760425Ab2D0Rlm (ORCPT ); Fri, 27 Apr 2012 13:41:42 -0400 Received: by qabg24 with SMTP id g24so83592qab.1 for ; Fri, 27 Apr 2012 10:41:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; bh=pKpYIdsD4e0zJXNZ2w9qoq5U1/i/zVTPDyipLqySaL4=; b=jehGR77Uu/PEPmel9gtxTRJp7o13ta6mHGFDBcPl6SulQWJDmcjCgfRnplcmoDBS4t nyEGq31VfMstNuRlMcA8RGDyzzPvBvpABE6NBJXvQ8yj5M0PMkVk2W3LFd5HHnn8MEcZ 5F1V/LMgZN3cppGj7bLQRFkmMFX/XgbRGbCSFSqIdDzRgp8C1NxGfhWORJJSoU21knNV aYVna0PeEk0iGkv0TZnvI93+1oJdV8ksDC5DMIQirsNdl3nmRpBaTNOJrZ1IC12eDbBx sbmrwlx6LCkvOWin+2DyCJG6kQxLCswLvCL1NQQ6pU0mKGkk6XND2JYOhFt3uZaOb8vO s8Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent :x-gm-message-state; bh=pKpYIdsD4e0zJXNZ2w9qoq5U1/i/zVTPDyipLqySaL4=; b=Uee9C9Dz1sMd9FVH9CBCI9tw/7ELA6hmH3szmxU0EIXk1QkFOPKPY86PSpB1Cy5tkR 4NBGgJLvuD2eJvw+Iowyh2Cg3eAb1wzYh56mWs9b4RkryugV3fVzyROxIr95swG2yqFR /8BV7J3MTTNUd2fQxFc7CVx9/QYJo0MO9Y1K+X1j17o5iMz5Zt8cuTp8nNYeTmOhftre OrI3fVR+3uFw3gbDzHRhxTfW3WVKAx9JhvoG5rGFzIaB72n/AyZd6b1elW89z3ZD76iP fOfz+s1aWx90nJpvUUO+ZUch74XeoBjjH1ORP+tQBgpgmlQ5u4PWCmQWFzwBPIcLaMo6 OGhg== Received: by 10.236.76.4 with SMTP id a4mr15202378yhe.2.1335548501697; Fri, 27 Apr 2012 10:41:41 -0700 (PDT) Received: by 10.236.76.4 with SMTP id a4mr15202349yhe.2.1335548501608; Fri, 27 Apr 2012 10:41:41 -0700 (PDT) Received: from wpzn4.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id d47si6995096yhl.6.2012.04.27.10.41.41 (version=TLSv1/SSLv3 cipher=AES128-SHA); Fri, 27 Apr 2012 10:41:41 -0700 (PDT) Received: from bhelgaas.mtv.corp.google.com (bhelgaas.mtv.corp.google.com [172.18.96.155]) by wpzn4.hot.corp.google.com (Postfix) with ESMTP id 6FCBC1E09BD; Fri, 27 Apr 2012 10:41:41 -0700 (PDT) Received: by bhelgaas.mtv.corp.google.com (Postfix, from userid 131485) id 1A4971801A1; Fri, 27 Apr 2012 10:41:41 -0700 (PDT) Date: Fri, 27 Apr 2012 11:41:41 -0600 From: Bjorn Helgaas To: "Hao, Xudong" Cc: "linux-pci@vger.kernel.org" , Don Dutile , Matthew Wilcox , "Zhang, Xiantao" Subject: Re: [PATCH v6] Quirk for IVB graphics FLR errata Message-ID: <20120427174141.GA11634@google.com> References: <403610A45A2B5242BD291EDAE8B37D300FD24698@SHSMSX102.ccr.corp.intel.com> <403610A45A2B5242BD291EDAE8B37D300FD3ABC3@SHSMSX101.ccr.corp.intel.com> <403610A45A2B5242BD291EDAE8B37D300FD8BEA9@SHSMSX102.ccr.corp.intel.com> <403610A45A2B5242BD291EDAE8B37D300FD906DD@SHSMSX102.ccr.corp.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <403610A45A2B5242BD291EDAE8B37D300FD906DD@SHSMSX102.ccr.corp.intel.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-Gm-Message-State: ALoCoQkcIkpgW9bv031nYc3eTKEXW4v3iLTO51kVXGBpLHYhVVwOvmGHsAUJERAjvIboGWGgdYjGiFfZV7KU0rQGQJHJM73ka0upd3lbT4PR5N/7GOrGS/oENhA8jUwSHYPNuWkCZEpym1Dn+2CO/z0OJv0jCJbmc/MoiCfxhQChxRat5yw1SSw= Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Fri, Apr 27, 2012 at 01:26:18AM +0000, Hao, Xudong wrote: > Maybe something configuration wrong on my mail client, I attach the patch as an attachment, can you open it in your side? Yes, I could open the attachment. But it makes it easier for everybody to read & review your patches if you can figure out how to post patches directly in the message rather than as an attachment. Here's an updated version of your patch. I changed the following: - Wrapped changelog text so it fits nicely for "git log". - Added #define for 0xd0100 offset (please supply a more useful name). - Used pci_iomap() and ioread32()/iowrite32(). - Used msleep() rather than spinning (Matthew suggested this earlier, but you apparently missed it). Note that I went back to your original "do {} while ()" structure to make sure we read PCH_PP_STATUS at least once. - Added message if reset times out. This is still x86-specific code that clutters all other architectures. We might fix this someday by adding a DECLARE_PCI_FIXUP_RESET(), so the IVB code could live in arch/x86, and the linker could still collect all the device-specific reset methods. But I haven't done that yet. Please test and comment on this (and supply a name for 0xd0100): commit 8566df6d83bf89c8cad3810d5d333a31a95b133e Author: Xudong Hao Date: Fri Apr 27 09:16:46 2012 -0600 PCI: work around IvyBridge internal graphics FLR erratum For IvyBridge Mobile platform, a system hang may occur if a FLR (Function Level Reset) is asserted to internal graphics. This quirk is a workaround for the IVB FLR errata issue. We are disabling the FLR reset handshake between the PCH and CPU display, then manually powering down the panel power sequencing and resetting the PCH display. Signed-off-by: Xudong Hao Signed-off-by: Kay, Allen M Signed-off-by: Matthew Wilcox --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 4bf7102..d5646de 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3085,16 +3085,74 @@ static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe) return 0; } +#include "../gpu/drm/i915/i915_reg.h" +#define MSG_CTL 0x45010 +#define XXXX 0xd0100 +#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ + +static int reset_ivb_igd(struct pci_dev *dev, int probe) +{ + void __iomem *mmio_base; + unsigned long timeout; + u32 val; + + if (probe) + return 0; + + mmio_base = pci_iomap(dev, 0, 0); + if (!mmio_base) + return -ENOMEM; + + iowrite32(0x00000002, mmio_base + MSG_CTL); + + /* + * Clobbering SOUTH_CHICKEN2 register is fine only if the next + * driver loaded sets the right bits. However, this's a reset and + * the bits have been set by i915 previously, so we clobber + * SOUTH_CHICKEN2 register directly here. + */ + iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); + + val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; + iowrite32(val, mmio_base + PCH_PP_CONTROL); + + timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); + do { + val = ioread32(mmio_base + PCH_PP_STATUS); + if ((val & 0xB0000000) == 0) + goto reset_complete; + msleep(10); + } while (time_before(jiffies, timeout)); + dev_warn(&dev->dev, "timeout during reset\n"); + +reset_complete: + iowrite32(0x00000002, mmio_base + XXXX); + + pci_iounmap(dev, mmio_base); + return 0; +} + #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed +#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 +#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, reset_intel_82599_sfp_virtfn }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, + reset_ivb_igd }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, + reset_ivb_igd }, { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, reset_intel_generic_dev }, { 0 } }; +/* + * These device-specific reset methods are here rather than in a driver + * because when a host assigns a device to a guest VM, the host may need + * to reset the device but probably doesn't have a driver for it. + */ int pci_dev_specific_reset(struct pci_dev *dev, int probe) { const struct pci_dev_reset_methods *i;