| Message ID | 1678080302-29691-4-git-send-email-quic_rohiagar@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add PCIe EP support for SDX65 | expand |
On 06/03/2023 07:24, Rohit Agarwal wrote: > Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is > used by the PCIe EP controller. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index b073e0c..246290d 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -292,6 +292,38 @@ > status = "disabled"; > }; > > + pcie0_phy: phy@1c07000 { > + compatible = "qcom,sdx65-qmp-pcie-phy"; > + reg = <0x01c07000 0x1e4>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, > + <&gcc GCC_PCIE_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_CLKREF_EN>, > + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; > + clock-names = "aux", "cfg_ahb", "ref", "refgen"; > + > + resets = <&gcc GCC_PCIE_PHY_BCR>; > + reset-names = "phy"; > + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; > + assigned-clock-rates = <100000000>; > + status = "disabled"; > + > + pcie0_lane: lanes@1c06000 { Please use new style bindings found in qcom,sc8280xp-qmp-pcie-phy.yaml > + reg = <0x01c06000 0xf0>, /* tx0 */ > + <0x01c06200 0x2f0>, /* rx0 */ > + <0x01c07200 0x1e8>, /* pcs */ > + <0x01c06800 0xf0>, /* tx1 */ > + <0x01c06a00 0x2f0>, /* rx1 */ > + <0x01c07400 0xc00>; /* pcs_misc */ > + clocks = <&gcc GCC_PCIE_PIPE_CLK>; > + clock-names = "pipe0"; > + #phy-cells = <0>; > + clock-output-names = "pcie_pipe_clk"; > + }; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x01f40000 0x40000>;
On 3/6/2023 2:11 PM, Dmitry Baryshkov wrote: > On 06/03/2023 07:24, Rohit Agarwal wrote: >> Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is >> used by the PCIe EP controller. >> >> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> >> --- >> arch/arm/boot/dts/qcom-sdx65.dtsi | 32 >> ++++++++++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi >> b/arch/arm/boot/dts/qcom-sdx65.dtsi >> index b073e0c..246290d 100644 >> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi >> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi >> @@ -292,6 +292,38 @@ >> status = "disabled"; >> }; >> + pcie0_phy: phy@1c07000 { >> + compatible = "qcom,sdx65-qmp-pcie-phy"; >> + reg = <0x01c07000 0x1e4>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, >> + <&gcc GCC_PCIE_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_0_CLKREF_EN>, >> + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; >> + clock-names = "aux", "cfg_ahb", "ref", "refgen"; >> + >> + resets = <&gcc GCC_PCIE_PHY_BCR>; >> + reset-names = "phy"; >> + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; >> + assigned-clock-rates = <100000000>; >> + status = "disabled"; >> + >> + pcie0_lane: lanes@1c06000 { > > Please use new style bindings found in qcom,sc8280xp-qmp-pcie-phy.yaml Sure, Will update it the bindings and this. Thanks, Rohit. > >> + reg = <0x01c06000 0xf0>, /* tx0 */ >> + <0x01c06200 0x2f0>, /* rx0 */ >> + <0x01c07200 0x1e8>, /* pcs */ >> + <0x01c06800 0xf0>, /* tx1 */ >> + <0x01c06a00 0x2f0>, /* rx1 */ >> + <0x01c07400 0xc00>; /* pcs_misc */ >> + clocks = <&gcc GCC_PCIE_PIPE_CLK>; >> + clock-names = "pipe0"; >> + #phy-cells = <0>; >> + clock-output-names = "pcie_pipe_clk"; >> + }; >> + }; >> + >> tcsr_mutex: hwlock@1f40000 { >> compatible = "qcom,tcsr-mutex"; >> reg = <0x01f40000 0x40000>; >
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index b073e0c..246290d 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -292,6 +292,38 @@ status = "disabled"; }; + pcie0_phy: phy@1c07000 { + compatible = "qcom,sdx65-qmp-pcie-phy"; + reg = <0x01c07000 0x1e4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + status = "disabled"; + + pcie0_lane: lanes@1c06000 { + reg = <0x01c06000 0xf0>, /* tx0 */ + <0x01c06200 0x2f0>, /* rx0 */ + <0x01c07200 0x1e8>, /* pcs */ + <0x01c06800 0xf0>, /* tx1 */ + <0x01c06a00 0x2f0>, /* rx1 */ + <0x01c07400 0xc00>; /* pcs_misc */ + clocks = <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "pipe0"; + #phy-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>;
Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is used by the PCIe EP controller. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm/boot/dts/qcom-sdx65.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)