| Message ID | 1644902192-12957-1-git-send-email-hongxing.zhu@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3,1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support | expand |
On Tue, Feb 15, 2022 at 01:16:31PM +0800, Richard Zhu wrote: > In the i.MX6QP sabresd board(sch-28857) design, one external oscillator > is powered up by vgen3 and used as the PCIe reference clock source by > the endpoint device. > > If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would > has to be in bypass mode, and ENET clocks would be messed up. > > To keep things simple, let RC use the internal PLL as reference clock > and set vgen3 always on to enable the external oscillator for endpoint > device on i.MX6QP sabresd board. > > NOTE: This reference clock setup is used to pass the GEN2 TX compliance > tests, and isn't recommended as a setup in the end-user design. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > --- > arch/arm/boot/dts/imx6qp-sabresd.dts | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts > index 480e73183f6b..083cf90bcab5 100644 > --- a/arch/arm/boot/dts/imx6qp-sabresd.dts > +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts > @@ -50,8 +50,14 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 > }; > }; > > +&vgen3_reg { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; These can be saved, as they are unchanged? Shawn > + regulator-always-on; > +}; > + > &pcie { > - status = "disabled"; > + status = "okay"; > }; > > &sata { > -- > 2.25.1 >
> -----Original Message----- > From: Shawn Guo <shawnguo@kernel.org> > Sent: 2022年2月21日 12:20 > To: Hongxing Zhu <hongxing.zhu@nxp.com> > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > lorenzo.pieralisi@arm.com; linux-pci@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [PATCH v3 1/2] ARM: dts: imx6qp-sabresd: Enable PCIe support > > On Tue, Feb 15, 2022 at 01:16:31PM +0800, Richard Zhu wrote: > > In the i.MX6QP sabresd board(sch-28857) design, one external > > oscillator is powered up by vgen3 and used as the PCIe reference clock > > source by the endpoint device. > > > > If RC uses this oscillator as reference clock too, PLL6(ENET PLL) > > would has to be in bypass mode, and ENET clocks would be messed up. > > > > To keep things simple, let RC use the internal PLL as reference clock > > and set vgen3 always on to enable the external oscillator for endpoint > > device on i.MX6QP sabresd board. > > > > NOTE: This reference clock setup is used to pass the GEN2 TX > > compliance tests, and isn't recommended as a setup in the end-user design. > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > --- > > arch/arm/boot/dts/imx6qp-sabresd.dts | 8 +++++++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts > > b/arch/arm/boot/dts/imx6qp-sabresd.dts > > index 480e73183f6b..083cf90bcab5 100644 > > --- a/arch/arm/boot/dts/imx6qp-sabresd.dts > > +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts > > @@ -50,8 +50,14 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 > 0x17059 > > }; > > }; > > > > +&vgen3_reg { > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <3300000>; > > These can be saved, as they are unchanged? Good caught. Thanks. These two lines would be removed, since they are not changed. Best Regards Richard Zhu > > Shawn > > > + regulator-always-on; > > +}; > > + > > &pcie { > > - status = "disabled"; > > + status = "okay"; > > }; > > > > &sata { > > -- > > 2.25.1 > >
diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts index 480e73183f6b..083cf90bcab5 100644 --- a/arch/arm/boot/dts/imx6qp-sabresd.dts +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts @@ -50,8 +50,14 @@ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 }; }; +&vgen3_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; +}; + &pcie { - status = "disabled"; + status = "okay"; }; &sata {
In the i.MX6QP sabresd board(sch-28857) design, one external oscillator is powered up by vgen3 and used as the PCIe reference clock source by the endpoint device. If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would has to be in bypass mode, and ENET clocks would be messed up. To keep things simple, let RC use the internal PLL as reference clock and set vgen3 always on to enable the external oscillator for endpoint device on i.MX6QP sabresd board. NOTE: This reference clock setup is used to pass the GEN2 TX compliance tests, and isn't recommended as a setup in the end-user design. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- arch/arm/boot/dts/imx6qp-sabresd.dts | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)