| Message ID | 1644390156-5940-2-git-send-email-hongxing.zhu@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | [RFC,1/2] ARM: dts: imx6qp-sabresd: Enable pcie support | expand |
s/pcie/PCIe/ and maybe s/imx6qp/i.MX6QP/ in the subject. Am Mittwoch, dem 09.02.2022 um 15:02 +0800 schrieb Richard Zhu: > i.MX6QP PCIe supports the RESET logic, thus it can support > the L2 exit by the reset mechanism. > Enable the i.MX6QP PCIe suspend/resume operations support. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Other than the nitpick: Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/pci/controller/dwc/pci-imx6.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 784801f2f9e6..62262483470a 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -995,6 +995,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) > /* Others poke directly at IOMUXC registers */ > switch (imx6_pcie->drvdata->variant) { > case IMX6SX: > + case IMX6QP: > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, > IMX6SX_GPR12_PCIE_PM_TURN_OFF, > IMX6SX_GPR12_PCIE_PM_TURN_OFF); > @@ -1307,7 +1308,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { > [IMX6QP] = { > .variant = IMX6QP, > .flags = IMX6_PCIE_FLAG_IMX6_PHY | > - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, > + IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | > + IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, > .dbi_length = 0x200, > }, > [IMX7D] = {
In subject, s/pcie/PCIe/ or remove it altogether, since I don't think it adds useful information. On Wed, Feb 09, 2022 at 03:02:36PM +0800, Richard Zhu wrote: > i.MX6QP PCIe supports the RESET logic, thus it can support > the L2 exit by the reset mechanism. > Enable the i.MX6QP PCIe suspend/resume operations support. Add blank line between paragraphs or rewrap into a single paragraph. Rewrap to fill 75 columns. What does "L2 exit by reset mechanism" mean? Is this an i.MX6-specific thing? If not, can you point me to the relevant part of the PCIe spec? Bjorn
> -----Original Message----- > From: Lucas Stach <l.stach@pengutronix.de> > Sent: 2022年2月9日 17:08 > To: Hongxing Zhu <hongxing.zhu@nxp.com>; bhelgaas@google.com; > lorenzo.pieralisi@arm.com; shawnguo@kernel.org > Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > <linux-imx@nxp.com> > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management > support > > s/pcie/PCIe/ and maybe s/imx6qp/i.MX6QP/ in the subject. Thanks, would be changed later. > > Am Mittwoch, dem 09.02.2022 um 15:02 +0800 schrieb Richard Zhu: > > i.MX6QP PCIe supports the RESET logic, thus it can support the L2 exit > > by the reset mechanism. > > Enable the i.MX6QP PCIe suspend/resume operations support. > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > Other than the nitpick: > Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Thanks. Best Regards Richard Zhu> > > --- > > drivers/pci/controller/dwc/pci-imx6.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c > > b/drivers/pci/controller/dwc/pci-imx6.c > > index 784801f2f9e6..62262483470a 100644 > > --- a/drivers/pci/controller/dwc/pci-imx6.c > > +++ b/drivers/pci/controller/dwc/pci-imx6.c > > @@ -995,6 +995,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie > *imx6_pcie) > > /* Others poke directly at IOMUXC registers */ > > switch (imx6_pcie->drvdata->variant) { > > case IMX6SX: > > + case IMX6QP: > > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, > > IMX6SX_GPR12_PCIE_PM_TURN_OFF, > > IMX6SX_GPR12_PCIE_PM_TURN_OFF); > > @@ -1307,7 +1308,8 @@ static const struct imx6_pcie_drvdata drvdata[] = > { > > [IMX6QP] = { > > .variant = IMX6QP, > > .flags = IMX6_PCIE_FLAG_IMX6_PHY | > > - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, > > + IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | > > + IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, > > .dbi_length = 0x200, > > }, > > [IMX7D] = { >
> -----Original Message----- > From: Bjorn Helgaas <helgaas@kernel.org> > Sent: 2022年2月9日 23:37 > To: Hongxing Zhu <hongxing.zhu@nxp.com> > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; linux-pci@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management > support > > In subject, s/pcie/PCIe/ or remove it altogether, since I don't think it adds > useful information. > > On Wed, Feb 09, 2022 at 03:02:36PM +0800, Richard Zhu wrote: > > i.MX6QP PCIe supports the RESET logic, thus it can support the L2 exit > > by the reset mechanism. > > Enable the i.MX6QP PCIe suspend/resume operations support. > > Add blank line between paragraphs or rewrap into a single paragraph. Got that, thanks. > > Rewrap to fill 75 columns. Okay, would be changed. > > What does "L2 exit by reset mechanism" mean? Is this an i.MX6-specific > thing? If not, can you point me to the relevant part of the PCIe spec? No, it's not i.MX6 specific thing. i.MX6Q/DL doesn't have the self-reset mechanism. Thus, it can't reset itself to an initialized stat when link exit from the L2 or L3 stats. i.MX6QP PCIe has the self-reset mechanism, and it can reset itself when link exit from L2 or L3 stats. The commit description might not accurate. How about change them to "i.MX6QP PCIe supports the RESET logic, thus it can reset itself to the initialized stat when exit from L2 or L3 stats." Best Regards Richard Zhu > > Bjorn
On Thu, Feb 10, 2022 at 03:23:19AM +0000, Hongxing Zhu wrote: > > -----Original Message----- > > From: Bjorn Helgaas <helgaas@kernel.org> > > Sent: 2022年2月9日 23:37 > > To: Hongxing Zhu <hongxing.zhu@nxp.com> > > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; linux-pci@vger.kernel.org; > > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com> > > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management > > support > > > > On Wed, Feb 09, 2022 at 03:02:36PM +0800, Richard Zhu wrote: > > > i.MX6QP PCIe supports the RESET logic, thus it can support the L2 exit > > > by the reset mechanism. > > > Enable the i.MX6QP PCIe suspend/resume operations support. > > What does "L2 exit by reset mechanism" mean? Is this an > > i.MX6-specific thing? If not, can you point me to the relevant > > part of the PCIe spec? > > No, it's not i.MX6 specific thing. i.MX6Q/DL doesn't have the > self-reset mechanism. Thus, it can't reset itself to an initialized > stat when link exit from the L2 or L3 stats. i.MX6QP PCIe has the > self-reset mechanism, and it can reset itself when link exit from L2 > or L3 stats. The commit description might not accurate. How about > change them to "i.MX6QP PCIe supports the RESET logic, thus it can > reset itself to the initialized stat when exit from L2 or L3 stats." s/stat/state/ Ugh, I have all sorts of questions now, but I don't think I want to know much more about this ;) Seems like this device requires software assist when bringing the link out of L2 or L3. Is that allowed per PCIe spec, or is this an erratum? Does this mean the driver needs to be involved when we take a device out of D3 (where the link was in L2 or L3)? Bjorn
> -----Original Message----- > From: Bjorn Helgaas <helgaas@kernel.org> > Sent: 2022年2月11日 6:05 > To: Hongxing Zhu <hongxing.zhu@nxp.com> > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; linux-pci@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management > support > > On Thu, Feb 10, 2022 at 03:23:19AM +0000, Hongxing Zhu wrote: > > > -----Original Message----- > > > From: Bjorn Helgaas <helgaas@kernel.org> > > > Sent: 2022年2月9日 23:37 > > > To: Hongxing Zhu <hongxing.zhu@nxp.com> > > > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > > > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; > > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > > > <linux-imx@nxp.com> > > > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power > > > management support > > > > > > On Wed, Feb 09, 2022 at 03:02:36PM +0800, Richard Zhu wrote: > > > > i.MX6QP PCIe supports the RESET logic, thus it can support the L2 > > > > exit by the reset mechanism. > > > > Enable the i.MX6QP PCIe suspend/resume operations support. > > > > What does "L2 exit by reset mechanism" mean? Is this an > > > i.MX6-specific thing? If not, can you point me to the relevant part > > > of the PCIe spec? > > > > No, it's not i.MX6 specific thing. i.MX6Q/DL doesn't have the > > self-reset mechanism. Thus, it can't reset itself to an initialized > > stat when link exit from the L2 or L3 stats. i.MX6QP PCIe has the > > self-reset mechanism, and it can reset itself when link exit from L2 > > or L3 stats. The commit description might not accurate. How about > > change them to "i.MX6QP PCIe supports the RESET logic, thus it can > > reset itself to the initialized stat when exit from L2 or L3 stats." > > s/stat/state/ Thanks for your quickly reply. Got that, would be changed later. > > Ugh, I have all sorts of questions now, but I don't think I want to know much > more about this ;) > > Seems like this device requires software assist when bringing the link out of L2 > or L3. Is that allowed per PCIe spec, or is this an erratum? > > Does this mean the driver needs to be involved when we take a device out of > D3 (where the link was in L2 or L3)? Yes, the SW should be involved when bringing the link out of L2 or L3. I looked through the SPEC, didn't find that they are forbidden by SPEC. It might be a design limitation, I think. Best Regards Richard Zhu > > Bjorn
[+cc Rafael, beginning of thread: https://lore.kernel.org/r/1644390156-5940-2-git-send-email-hongxing.zhu@nxp.com] On Fri, Feb 11, 2022 at 02:05:24AM +0000, Hongxing Zhu wrote: > > -----Original Message----- > > From: Bjorn Helgaas <helgaas@kernel.org> > > Sent: 2022年2月11日 6:05 > > To: Hongxing Zhu <hongxing.zhu@nxp.com> > > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; linux-pci@vger.kernel.org; > > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com> > > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management > > support > > > > On Thu, Feb 10, 2022 at 03:23:19AM +0000, Hongxing Zhu wrote: > > > > -----Original Message----- > > > > From: Bjorn Helgaas <helgaas@kernel.org> > > > > Sent: 2022年2月9日 23:37 > > > > To: Hongxing Zhu <hongxing.zhu@nxp.com> > > > > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > > > > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; > > > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > > > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > > > > <linux-imx@nxp.com> > > > > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power > > > > management support > > > > > > > > On Wed, Feb 09, 2022 at 03:02:36PM +0800, Richard Zhu wrote: > > > > > i.MX6QP PCIe supports the RESET logic, thus it can support the L2 > > > > > exit by the reset mechanism. > > > > > Enable the i.MX6QP PCIe suspend/resume operations support. > > > > > > What does "L2 exit by reset mechanism" mean? Is this an > > > > i.MX6-specific thing? If not, can you point me to the relevant part > > > > of the PCIe spec? > > > > > > No, it's not i.MX6 specific thing. i.MX6Q/DL doesn't have the > > > self-reset mechanism. Thus, it can't reset itself to an initialized > > > stat when link exit from the L2 or L3 stats. i.MX6QP PCIe has the > > > self-reset mechanism, and it can reset itself when link exit from L2 > > > or L3 stats. The commit description might not accurate. How about > > > change them to "i.MX6QP PCIe supports the RESET logic, thus it can > > > reset itself to the initialized stat when exit from L2 or L3 stats." > > > > Ugh, I have all sorts of questions now, but I don't think I want > > to know much more about this ;) > > > > Seems like this device requires software assist when bringing the > > link out of L2 or L3. Is that allowed per PCIe spec, or is this > > an erratum? > > > > Does this mean the driver needs to be involved when we take a > > device out of D3 (where the link was in L2 or L3)? > > Yes, the SW should be involved when bringing the link out of L2 or > L3. I looked through the SPEC, didn't find that they are forbidden > by SPEC. It might be a design limitation, I think. OK. I don't understand all the details of L2 and L3, so I'll take your word for it that this is allowed by spec. The case I was wondering about is when software puts a device in D3hot, which can be done via pci_set_power_state(), without any help from the imx6 driver. What state will the link be in, and can we also put the device back in D0 without help from imx6? Sec 5.3.2 says L1 is a permissible link state for D3hot, so maybe L2 and L3 are not involved in this case. Bjorn
> -----Original Message----- > From: Bjorn Helgaas <helgaas@kernel.org> > Sent: 2022年2月12日 0:53 > To: Hongxing Zhu <hongxing.zhu@nxp.com> > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; linux-pci@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>; Rafael J. Wysocki > <rjw@rjwysocki.net> > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power management > support > > [+cc Rafael, beginning of thread: > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ker > nel.org%2Fr%2F1644390156-5940-2-git-send-email-hongxing.zhu%40nxp.com > &data=04%7C01%7Chongxing.zhu%40nxp.com%7Ca40c2a3d7c03497f8c > f208d9ed7f0463%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63 > 7801952076367918%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD > AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata= > BnzoSbb92HEw%2BQAMspyCT72787aFUhmPiZX2ZVAztJo%3D&reserved > =0] > > On Fri, Feb 11, 2022 at 02:05:24AM +0000, Hongxing Zhu wrote: > > > -----Original Message----- > > > From: Bjorn Helgaas <helgaas@kernel.org> > > > Sent: 2022年2月11日 6:05 > > > To: Hongxing Zhu <hongxing.zhu@nxp.com> > > > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > > > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; > > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > > > <linux-imx@nxp.com> > > > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power > > > management support > > > > > > On Thu, Feb 10, 2022 at 03:23:19AM +0000, Hongxing Zhu wrote: > > > > > -----Original Message----- > > > > > From: Bjorn Helgaas <helgaas@kernel.org> > > > > > Sent: 2022年2月9日 23:37 > > > > > To: Hongxing Zhu <hongxing.zhu@nxp.com> > > > > > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > > > > > lorenzo.pieralisi@arm.com; shawnguo@kernel.org; > > > > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > > > > linux-kernel@vger.kernel.org; kernel@pengutronix.de; > > > > > dl-linux-imx <linux-imx@nxp.com> > > > > > Subject: Re: [RFC 2/2] PCI: imx6: Enable imx6qp pcie power > > > > > management support > > > > > > > > > > On Wed, Feb 09, 2022 at 03:02:36PM +0800, Richard Zhu wrote: > > > > > > i.MX6QP PCIe supports the RESET logic, thus it can support the > > > > > > L2 exit by the reset mechanism. > > > > > > Enable the i.MX6QP PCIe suspend/resume operations support. > > > > > > > > What does "L2 exit by reset mechanism" mean? Is this an > > > > > i.MX6-specific thing? If not, can you point me to the relevant > > > > > part of the PCIe spec? > > > > > > > > No, it's not i.MX6 specific thing. i.MX6Q/DL doesn't have the > > > > self-reset mechanism. Thus, it can't reset itself to an > > > > initialized stat when link exit from the L2 or L3 stats. i.MX6QP > > > > PCIe has the self-reset mechanism, and it can reset itself when > > > > link exit from L2 or L3 stats. The commit description might not > > > > accurate. How about change them to "i.MX6QP PCIe supports the > > > > RESET logic, thus it can reset itself to the initialized stat when exit from L2 > or L3 stats." > > > > > > Ugh, I have all sorts of questions now, but I don't think I want to > > > know much more about this ;) > > > > > > Seems like this device requires software assist when bringing the > > > link out of L2 or L3. Is that allowed per PCIe spec, or is this an > > > erratum? > > > > > > Does this mean the driver needs to be involved when we take a device > > > out of D3 (where the link was in L2 or L3)? > > > > Yes, the SW should be involved when bringing the link out of L2 or L3. > > I looked through the SPEC, didn't find that they are forbidden by > > SPEC. It might be a design limitation, I think. > > OK. I don't understand all the details of L2 and L3, so I'll take your word for it > that this is allowed by spec. > > The case I was wondering about is when software puts a device in D3hot, > which can be done via pci_set_power_state(), without any help from the imx6 > driver. What state will the link be in, and can we also put the device back in > D0 without help from imx6? Hi Bjorn: Regarding my understand, i.MX6QP PCIe would broadcast the PME message, handshake with remote EP, let link state to be L1 or L2/L3. Then, the EP device driver would put the device into D3 mode accordingly. Since i.MX PCIe doesn't support the L2 and the beacon to exit the L2 link power state. The reset and link retraining would be done to re-setup the link when exit the L3 link power state. Best Regards Richard > > Sec 5.3.2 says L1 is a permissible link state for D3hot, so maybe L2 and L3 are > not involved in this case. > > Bjorn
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 784801f2f9e6..62262483470a 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -995,6 +995,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) /* Others poke directly at IOMUXC registers */ switch (imx6_pcie->drvdata->variant) { case IMX6SX: + case IMX6QP: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF, IMX6SX_GPR12_PCIE_PM_TURN_OFF); @@ -1307,7 +1308,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { [IMX6QP] = { .variant = IMX6QP, .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, + IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | + IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length = 0x200, }, [IMX7D] = {
i.MX6QP PCIe supports the RESET logic, thus it can support the L2 exit by the reset mechanism. Enable the i.MX6QP PCIe suspend/resume operations support. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)