diff mbox series

[v2] PCI: dwc: Add upper limit address for outbound iATU

Message ID 1609930210-19227-1-git-send-email-shradha.t@samsung.com
State New
Headers show
Series [v2] PCI: dwc: Add upper limit address for outbound iATU | expand

Commit Message

Shradha Todi Jan. 6, 2021, 10:50 a.m. UTC 
The size parameter is unsigned long type which can accept size > 4GB. In
that case, the upper limit address must be programmed. Add support to
program the upper limit address and set INCREASE_REGION_SIZE in case size >
4GB.

Signed-off-by: Shradha Todi <shradha.t@samsung.com>
---
v1: https://lkml.org/lkml/2020/12/20/187
v2:
   Addressed Rob's review comment and added PCI version check condition to
   avoid writing to reserved registers.

 drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
 drivers/pci/controller/dwc/pcie-designware.h | 1 +
 2 files changed, 8 insertions(+), 2 deletions(-)

Comments

Pankaj Dubey Jan. 6, 2021, 11:31 a.m. UTC | #1 
> -----Original Message-----
> From: Shradha Todi <shradha.t@samsung.com>
> Sent: Wednesday, January 6, 2021 4:20 PM
> To: linux-kernel@vger.kernel.org; linux-pci@vger.kernel.org
> Cc: jingoohan1@gmail.com; gustavo.pimentel@synopsys.com;
> robh@kernel.org; lorenzo.pieralisi@arm.com; bhelgaas@google.com;
> pankaj.dubey@samsung.com; sriram.dash@samsung.com;
> niyas.ahmed@samsung.com; p.rajanbabu@samsung.com;
> l.mehra@samsung.com; hari.tv@samsung.com; Shradha Todi
> <shradha.t@samsung.com>
> Subject: [PATCH v2] PCI: dwc: Add upper limit address for outbound iATU
> 
> The size parameter is unsigned long type which can accept size > 4GB. In that
> case, the upper limit address must be programmed. Add support to program
> the upper limit address and set INCREASE_REGION_SIZE in case size > 4GB.
> 
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> ---
> v1: https://lkml.org/lkml/2020/12/20/187
> v2:
>    Addressed Rob's review comment and added PCI version check condition
> to
>    avoid writing to reserved registers.
> 

Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>

>  drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c
> b/drivers/pci/controller/dwc/pcie-designware.c
> index 74590c7..1d62ca9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -290,12 +290,17 @@ static void __dw_pcie_prog_outbound_atu(struct
> dw_pcie *pci, u8 func_no,
>  			   upper_32_bits(cpu_addr));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
>  			   lower_32_bits(cpu_addr + size - 1));
> +	if (pci->version >= 0x460A)
> +		dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
> +				   upper_32_bits(cpu_addr + size - 1));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
>  			   lower_32_bits(pci_addr));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
>  			   upper_32_bits(pci_addr));
> -	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
> -			   PCIE_ATU_FUNC_NUM(func_no));
> +	val = type | PCIE_ATU_FUNC_NUM(func_no);
> +	val = ((upper_32_bits(size - 1)) && (pci->version >= 0x460A)) ?
> +		val | PCIE_ATU_INCREASE_REGION_SIZE : val;
> +	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
> 
>  	/*
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h
> b/drivers/pci/controller/dwc/pcie-designware.h
> index 8b905a2..7da79eb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -102,6 +102,7 @@
>  #define PCIE_ATU_DEV(x)			FIELD_PREP(GENMASK(23,
> 19), x)
>  #define PCIE_ATU_FUNC(x)		FIELD_PREP(GENMASK(18, 16), x)
>  #define PCIE_ATU_UPPER_TARGET		0x91C
> +#define PCIE_ATU_UPPER_LIMIT		0x924
> 
>  #define PCIE_MISC_CONTROL_1_OFF		0x8BC
>  #define PCIE_DBI_RO_WR_EN		BIT(0)
> --
> 2.7.4
Shradha Todi Jan. 27, 2021, 9:16 a.m. UTC | #2 
Hi,
Gentle Ping..

Thanks

> -----Original Message-----
> From: Shradha Todi <shradha.t@samsung.com>
> Sent: Wednesday, January 6, 2021 4:20 PM
> Subject: [PATCH v2] PCI: dwc: Add upper limit address for outbound iATU
> 
> The size parameter is unsigned long type which can accept size > 4GB. In that
> case, the upper limit address must be programmed. Add support to program the
> upper limit address and set INCREASE_REGION_SIZE in case size > 4GB.
> 
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> ---
> v1: https://lkml.org/lkml/2020/12/20/187
> v2:
>    Addressed Rob's review comment and added PCI version check condition to
>    avoid writing to reserved registers.
> 
>  drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c
> b/drivers/pci/controller/dwc/pcie-designware.c
> index 74590c7..1d62ca9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -290,12 +290,17 @@ static void __dw_pcie_prog_outbound_atu(struct
> dw_pcie *pci, u8 func_no,
>  			   upper_32_bits(cpu_addr));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
>  			   lower_32_bits(cpu_addr + size - 1));
> +	if (pci->version >= 0x460A)
> +		dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
> +				   upper_32_bits(cpu_addr + size - 1));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
>  			   lower_32_bits(pci_addr));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
>  			   upper_32_bits(pci_addr));
> -	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
> -			   PCIE_ATU_FUNC_NUM(func_no));
> +	val = type | PCIE_ATU_FUNC_NUM(func_no);
> +	val = ((upper_32_bits(size - 1)) && (pci->version >= 0x460A)) ?
> +		val | PCIE_ATU_INCREASE_REGION_SIZE : val;
> +	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
> 
>  	/*
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h
> b/drivers/pci/controller/dwc/pcie-designware.h
> index 8b905a2..7da79eb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -102,6 +102,7 @@
>  #define PCIE_ATU_DEV(x)			FIELD_PREP(GENMASK(23, 19),
> x)
>  #define PCIE_ATU_FUNC(x)		FIELD_PREP(GENMASK(18, 16), x)
>  #define PCIE_ATU_UPPER_TARGET		0x91C
> +#define PCIE_ATU_UPPER_LIMIT		0x924
> 
>  #define PCIE_MISC_CONTROL_1_OFF		0x8BC
>  #define PCIE_DBI_RO_WR_EN		BIT(0)
> --
> 2.7.4
Rob Herring (Arm) Jan. 27, 2021, 5:39 p.m. UTC | #3 
On Wed, Jan 6, 2021 at 4:52 AM Shradha Todi <shradha.t@samsung.com> wrote:
>
> The size parameter is unsigned long type which can accept size > 4GB. In
> that case, the upper limit address must be programmed. Add support to
> program the upper limit address and set INCREASE_REGION_SIZE in case size >
> 4GB.
>
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> ---
> v1: https://lkml.org/lkml/2020/12/20/187
> v2:
>    Addressed Rob's review comment and added PCI version check condition to
>    avoid writing to reserved registers.
>
>  drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
>  drivers/pci/controller/dwc/pcie-designware.h | 1 +
>  2 files changed, 8 insertions(+), 2 deletions(-)

Reviewed-by: Rob Herring <robh@kernel.org>
Lorenzo Pieralisi Feb. 1, 2021, 6:57 p.m. UTC | #4 
On Wed, Jan 06, 2021 at 04:20:10PM +0530, Shradha Todi wrote:
> The size parameter is unsigned long type which can accept size > 4GB. In
> that case, the upper limit address must be programmed. Add support to
> program the upper limit address and set INCREASE_REGION_SIZE in case size >
> 4GB.
> 
> Signed-off-by: Shradha Todi <shradha.t@samsung.com>
> ---
> v1: https://lkml.org/lkml/2020/12/20/187
> v2:
>    Addressed Rob's review comment and added PCI version check condition to
>    avoid writing to reserved registers.
> 
>  drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++--
>  drivers/pci/controller/dwc/pcie-designware.h | 1 +
>  2 files changed, 8 insertions(+), 2 deletions(-)

Does not apply to my pci/dwc branch, please rebase it on top of it
and resend it while keeping review tags.

Thanks,
Lorenzo

> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 74590c7..1d62ca9 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -290,12 +290,17 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
>  			   upper_32_bits(cpu_addr));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
>  			   lower_32_bits(cpu_addr + size - 1));
> +	if (pci->version >= 0x460A)
> +		dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
> +				   upper_32_bits(cpu_addr + size - 1));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
>  			   lower_32_bits(pci_addr));
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
>  			   upper_32_bits(pci_addr));
> -	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
> -			   PCIE_ATU_FUNC_NUM(func_no));
> +	val = type | PCIE_ATU_FUNC_NUM(func_no);
> +	val = ((upper_32_bits(size - 1)) && (pci->version >= 0x460A)) ?
> +		val | PCIE_ATU_INCREASE_REGION_SIZE : val;
> +	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
>  
>  	/*
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 8b905a2..7da79eb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -102,6 +102,7 @@
>  #define PCIE_ATU_DEV(x)			FIELD_PREP(GENMASK(23, 19), x)
>  #define PCIE_ATU_FUNC(x)		FIELD_PREP(GENMASK(18, 16), x)
>  #define PCIE_ATU_UPPER_TARGET		0x91C
> +#define PCIE_ATU_UPPER_LIMIT		0x924
>  
>  #define PCIE_MISC_CONTROL_1_OFF		0x8BC
>  #define PCIE_DBI_RO_WR_EN		BIT(0)
> -- 
> 2.7.4
>
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 74590c7..1d62ca9 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -290,12 +290,17 @@  static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
 			   upper_32_bits(cpu_addr));
 	dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
 			   lower_32_bits(cpu_addr + size - 1));
+	if (pci->version >= 0x460A)
+		dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT,
+				   upper_32_bits(cpu_addr + size - 1));
 	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
 			   lower_32_bits(pci_addr));
 	dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
 			   upper_32_bits(pci_addr));
-	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
-			   PCIE_ATU_FUNC_NUM(func_no));
+	val = type | PCIE_ATU_FUNC_NUM(func_no);
+	val = ((upper_32_bits(size - 1)) && (pci->version >= 0x460A)) ?
+		val | PCIE_ATU_INCREASE_REGION_SIZE : val;
+	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val);
 	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
 
 	/*
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 8b905a2..7da79eb 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -102,6 +102,7 @@ 
 #define PCIE_ATU_DEV(x)			FIELD_PREP(GENMASK(23, 19), x)
 #define PCIE_ATU_FUNC(x)		FIELD_PREP(GENMASK(18, 16), x)
 #define PCIE_ATU_UPPER_TARGET		0x91C
+#define PCIE_ATU_UPPER_LIMIT		0x924
 
 #define PCIE_MISC_CONTROL_1_OFF		0x8BC
 #define PCIE_DBI_RO_WR_EN		BIT(0)