From patchwork Fri May 15 04:48:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 1290845 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=socionext.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49NbXR0dTLz9sRf for ; Fri, 15 May 2020 14:48:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725899AbgEOEsg (ORCPT ); Fri, 15 May 2020 00:48:36 -0400 Received: from mx.socionext.com ([202.248.49.38]:25905 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725968AbgEOEsf (ORCPT ); Fri, 15 May 2020 00:48:35 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 15 May 2020 13:48:34 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 52C7460057; Fri, 15 May 2020 13:48:34 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 15 May 2020 13:48:34 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id B49981A0E67; Fri, 15 May 2020 13:48:33 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 1/5] PCI: dwc: Add msi_host_isr() callback Date: Fri, 15 May 2020 13:48:21 +0900 Message-Id: <1589518105-18368-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589518105-18368-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1589518105-18368-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This adds msi_host_isr() callback function support to describe SoC-dependent service triggered by MSI. For example, when AER interrupt is triggered by MSI, the callback function reads SoC-dependent registers and detects that the interrupt is from AER, and invoke AER interrupts related to MSI. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++---- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0f36a92..491b7a8 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -110,13 +110,13 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) static void dw_chained_msi_isr(struct irq_desc *desc) { struct irq_chip *chip = irq_desc_get_chip(desc); - struct pcie_port *pp; + struct pcie_port *pp = irq_desc_get_handler_data(desc); - chained_irq_enter(chip, desc); + if (pp->ops->msi_host_isr) + pp->ops->msi_host_isr(pp); - pp = irq_desc_get_handler_data(desc); + chained_irq_enter(chip, desc); dw_handle_msi_irq(pp); - chained_irq_exit(chip, desc); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 5a18e94..27fee10 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -160,6 +160,7 @@ struct dw_pcie_host_ops { void (*scan_bus)(struct pcie_port *pp); void (*set_num_vectors)(struct pcie_port *pp); int (*msi_host_init)(struct pcie_port *pp); + void (*msi_host_isr)(struct pcie_port *pp); }; struct pcie_port {