From patchwork Tue Jan 14 07:22:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 1222537 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 47xhx04h5nz9sPW for ; Tue, 14 Jan 2020 18:32:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728992AbgANHcD (ORCPT ); Tue, 14 Jan 2020 02:32:03 -0500 Received: from lucky1.263xmail.com ([211.157.147.134]:51072 "EHLO lucky1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728734AbgANHcD (ORCPT ); Tue, 14 Jan 2020 02:32:03 -0500 Received: from localhost (unknown [192.168.167.16]) by lucky1.263xmail.com (Postfix) with ESMTP id 983A34D08A; Tue, 14 Jan 2020 15:24:24 +0800 (CST) X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P5437T140292994864896S1578986620990337_; Tue, 14 Jan 2020 15:24:25 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <808cfcb29a022183481baf5b4f977dfe> X-RL-SENDER: shawn.lin@rock-chips.com X-SENDER: lintao@rock-chips.com X-LOGIN-NAME: shawn.lin@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 From: Shawn Lin To: Heiko Stuebner , Lorenzo Pieralisi , Rob Herring , Kishon Vijay Abraham I , Bjorn Helgaas Cc: Jingoo Han , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, William Wu , Simon Xue , linux-rockchip@lists.infradead.org, Shawn Lin Subject: [PATCH 3/6] PCI: dwc: Skip allocating own MSI domain if using external MSI domain Date: Tue, 14 Jan 2020 15:22:57 +0800 Message-Id: <1578986580-71974-4-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1578986580-71974-1-git-send-email-shawn.lin@rock-chips.com> References: <1578986580-71974-1-git-send-email-shawn.lin@rock-chips.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On some platform, external MSI domain is using instead of the one created by designware driver. For instance, if using GIC-V3-ITS as a MSI domain, we only need set msi-map in the devicetree but never need any bit in the designware driver to handle MSI stuff. So skip allocating its own MSI domain for that case. Signed-off-by: Shawn Lin Signed-off-by: Simon Xue --- drivers/pci/controller/dwc/pcie-designware-host.c | 10 +++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 395feb8..e78d094 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -257,6 +257,10 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); + /* Rely on the external MSI domain */ + if (pp->msi_ext) + return 0; + pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp); if (!pp->irq_domain) { @@ -278,6 +282,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) void dw_pcie_free_msi(struct pcie_port *pp) { + if (pp->msi_ext) + return; + if (pp->msi_irq) { irq_set_chained_handler(pp->msi_irq, NULL); irq_set_handler_data(pp->msi_irq, NULL); @@ -413,7 +420,8 @@ int dw_pcie_host_init(struct pcie_port *pp) if (ret) pci->num_viewport = 2; - if (pci_msi_enabled()) { + if (pci_msi_enabled() && + !pp->msi_ext) { /* * If a specific SoC driver needs to change the * default number of vectors, it needs to implement diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index a22ea59..eeafa52 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -201,6 +201,7 @@ struct pcie_port { u32 irq_mask[MAX_MSI_CTRLS]; struct pci_bus *root_bus; raw_spinlock_t lock; + int msi_ext; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); };