diff mbox series

[1/2] lspci: Decode Multicast Extended Capability

Message ID 154154115111.78911.820638647771761075.stgit@bhelgaas-glaptop.roam.corp.google.com
State Not Applicable
Headers show
Series lspci: Decode Multicast capability | expand

Commit Message

Bjorn Helgaas Nov. 6, 2018, 9:52 p.m. UTC 
From: Bjorn Helgaas <bhelgaas@google.com>

Decode the Multicast Extended Capability described in PCIe r4.0, sec
7.9.11.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
 lib/header.h        |   18 ++++
 ls-ecaps.c          |   59 ++++++++++++
 tests/cap-multicast |  257 +++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 334 insertions(+)
 create mode 100644 tests/cap-multicast
diff mbox series

Patch

diff --git a/lib/header.h b/lib/header.h
index d785473..b563073 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1095,6 +1095,24 @@ 
 #define PCI_IOV_MSA_BIR(x)	((x) & 7) /* VF Migration State BIR */
 #define PCI_IOV_MSA_OFFSET(x)	((x) & 0xfffffff8) /* VF Migration State Offset */
 
+/* Multicast */
+#define PCI_MCAST_CAP		0x04	/* Multicast Capability */
+#define  PCI_MCAST_CAP_MAX_GROUP(x) ((x) & 0x3f)
+#define  PCI_MCAST_CAP_WIN_SIZE(x) (((x) >> 8) & 0x3f)
+#define  PCI_MCAST_CAP_ECRC	0x8000	/* ECRC Regeneration Supported */
+#define PCI_MCAST_CTRL		0x06	/* Multicast Control */
+#define  PCI_MCAST_CTRL_NUM_GROUP(x) ((x) & 0x3f)
+#define  PCI_MCAST_CTRL_ENABLE	0x8000	/* MC Enabled */
+#define PCI_MCAST_BAR		0x08	/* Base Address */
+#define  PCI_MCAST_BAR_INDEX_POS(x)	((u32) ((x) & 0x3f))
+#define  PCI_MCAST_BAR_MASK	(~0xfffUL)
+#define PCI_MCAST_RCV		0x10	/* Receive */
+#define PCI_MCAST_BLOCK		0x18	/* Block All */
+#define PCI_MCAST_BLOCK_UNTRANS	0x20	/* Block Untranslated */
+#define PCI_MCAST_OVL_BAR	0x28	/* Overlay BAR */
+#define  PCI_MCAST_OVL_SIZE(x)	((u32) ((x) & 0x3f))
+#define  PCI_MCAST_OVL_MASK	(~0x3fUL)
+
 /* Page Request Interface */
 #define PCI_PRI_CTRL		0x04	/* PRI Control Register */
 #define  PCI_PRI_CTRL_ENABLE	0x01	/* Enable */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index 5505948..3deb535 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -396,6 +396,62 @@  cap_sriov(struct device *d, int where)
 	PCI_IOV_MSA_BIR(l));
 }
 
+static void
+cap_multicast(struct device *d, int where, int type)
+{
+  u16 w;
+  u32 l;
+  u64 bar, rcv, block;
+
+  printf("Multicast\n");
+  if (verbose < 2)
+    return;
+
+  if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
+    return;
+
+  w = get_conf_word(d, where + PCI_MCAST_CAP);
+  printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
+  if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
+    printf(", WindowSz %d (%d bytes)",
+      PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
+  if (type == PCI_EXP_TYPE_ROOT_PORT ||
+      type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
+    printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
+  w = get_conf_word(d, where + PCI_MCAST_CTRL);
+  printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
+    PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
+  bar = get_conf_long(d, where + PCI_MCAST_BAR);
+  l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
+  bar |= (u64) l << 32;
+  printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
+    PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
+  rcv = get_conf_long(d, where + PCI_MCAST_RCV);
+  l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
+  rcv |= (u64) l << 32;
+  printf("\t\tMcastReceiveVec:      %016" PCI_U64_FMT_X "\n", rcv);
+  block = get_conf_long(d, where + PCI_MCAST_BLOCK);
+  l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
+  block |= (u64) l << 32;
+  printf("\t\tMcastBlockAllVec:     %016" PCI_U64_FMT_X "\n", block);
+  block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
+  l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
+  block |= (u64) l << 32;
+  printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
+
+  if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
+    return;
+  bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
+  l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
+  bar |= (u64) l << 32;
+  printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
+  if (PCI_MCAST_OVL_SIZE(bar) >= 6)
+    printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
+  else
+    printf("(disabled)");
+  printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
+}
+
 static void
 cap_vc(struct device *d, int where)
 {
@@ -789,6 +845,9 @@  show_ext_caps(struct device *d, int type)
 	  case PCI_EXT_CAP_ID_MRIOV:
 	    printf("Multi-Root I/O Virtualization <?>\n");
 	    break;
+	  case PCI_EXT_CAP_ID_MCAST:
+	    cap_multicast(d, where, type);
+	    break;
 	  case PCI_EXT_CAP_ID_PRI:
 	    cap_pri(d, where);
 	    break;
diff --git a/tests/cap-multicast b/tests/cap-multicast
new file mode 100644
index 0000000..3fd2c31
--- /dev/null
+++ b/tests/cap-multicast
@@ -0,0 +1,257 @@ 
+07:00.0 PCI bridge: PLX Technology, Inc. Device 8796 (rev ab)
+00: b5 10 96 87 07 01 10 48 ab 00 04 06 08 00 01 00
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