From patchwork Wed May 23 20:18:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Meyer X-Patchwork-Id: 919392 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=gigaio.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gigaio-com.20150623.gappssmtp.com header.i=@gigaio-com.20150623.gappssmtp.com header.b="a/TAPImk"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40rkP55blmz9s16 for ; Thu, 24 May 2018 06:18:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933737AbeEWUSs (ORCPT ); Wed, 23 May 2018 16:18:48 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:37119 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934835AbeEWUSo (ORCPT ); Wed, 23 May 2018 16:18:44 -0400 Received: by mail-pl0-f67.google.com with SMTP id w19-v6so13686688plq.4 for ; Wed, 23 May 2018 13:18:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gigaio-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=34V4fJr1o872PtTlo8TS+BvpyeGGPbClSovU7ERZvpI=; b=a/TAPImkvuLLJezc5zM5tlkywwr8EjI8xKRm69smXS9l2GV4OxhGqeRM8/RhzGw4vR 6sVmRBRA1RzcJmPK1GT1jNFkJWlvli9JH73jFbhdjUGycq9U+PWX5wWJom+4xTOmP4yL 222NyGvXGuVBjtibrTOKXn+grwpw/i9Rs2pBWFU338VKbNifZ+RkHGGKvAfQcDBi4wtj xXhglPB30q4sojbh7El/xpNrYV3evDX04Joq/5+Qe7vIOWgjtZgAWDjdbUlKriMPsf6O MP7ZdPA/LqiCGaSZR1n32PuVUuI9sd9p5RGQMcm3gS6BXu72RP00q+v7fI6B8gysvUx+ u1tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=34V4fJr1o872PtTlo8TS+BvpyeGGPbClSovU7ERZvpI=; b=Bo6RlI0J+mSmIWMxYhDFSO3bYPI5zosOuslxkSx+JoZFrZrJOCNd7wi6bbzg3lbMf/ TDmt9GgZ9mWEneqKnRPUi8aaP73YpdnXDhwkO1/5tAdkLZHiSD9vIoGFb/Jt/ZDEFG9N mKr18XGAIawr+pDVkTF63USEXk6Hi/KwJUeqCTI9o36CNt62DSms2UFxTnhgnm0YSvTz UjxGlm5gEPoeqnEKAmec4TvF6ek49RdnxuUINaLgrrqop+xm679lvE21w2d9FbVlWyQx AiuiSv4+BkjELqSPp7d/Hm+C3ql+dgeD9VoM9jtBKk69dqiPftl3Duk/xEiys3TqU6cF HBvQ== X-Gm-Message-State: ALKqPwfH9QYoKdS21pn6B8zyVOiSdJoJcQNCowQhBj+xASl2VB3PAf/j IQGUXBlntX3r6iQcPfcxWvVprw== X-Google-Smtp-Source: AB8JxZqLwDPcTpRPmIt2q37ZSJ4+TEOaHgawEXg2KiOkxuUaQN0iK88Fd/zlzK9y2mBgEc3tdHAG4g== X-Received: by 2002:a17:902:bd84:: with SMTP id q4-v6mr4406806pls.254.1527106724376; Wed, 23 May 2018 13:18:44 -0700 (PDT) Received: from stryx3.evonexus.local ([69.43.204.50]) by smtp.gmail.com with ESMTPSA id f78-v6sm37831091pfk.138.2018.05.23.13.18.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 May 2018 13:18:43 -0700 (PDT) From: dmeyer@gigaio.com To: logang@deltatee.com, kurt.schwemmer@microsemi.com, linux-pci@vger.kernel.org, linux-ntb@googlegroups.com Cc: bhelgaas@google.com, jdmason@kudzu.us, dave.jiang@intel.com, allenbh@gmail.com, linux-kernel@vger.kernel.org, Doug Meyer Subject: [PATCH v2 1/2] NTB: Migrate PCI Constants to Cannonical PCI Header Date: Wed, 23 May 2018 13:18:05 -0700 Message-Id: <1527106686-18852-2-git-send-email-dmeyer@gigaio.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1527106686-18852-1-git-send-email-dmeyer@gigaio.com> References: <1527106686-18852-1-git-send-email-dmeyer@gigaio.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Doug Meyer This is the first of two patches to implement a PCI quirk which will allow the Switchtec NTB code to work with the IOMMU turned on. Here, the Microsemi Switchtec PCI vendor and device ID constants are moved to the canonical location in pci_ids.h. Also, Microsemi class constants are replaced with the standard PCI usage. Signed-off-by: Doug Meyer Reviewed-by: Logan Gunthorpe --- drivers/ntb/hw/mscc/ntb_hw_switchtec.c | 3 ++- drivers/pci/switch/switchtec.c | 15 +++++++-------- include/linux/pci_ids.h | 32 ++++++++++++++++++++++++++++++++ include/linux/switchtec.h | 4 ---- 4 files changed, 41 insertions(+), 13 deletions(-) diff --git a/drivers/ntb/hw/mscc/ntb_hw_switchtec.c b/drivers/ntb/hw/mscc/ntb_hw_switchtec.c index f624ae2..5ee5f40 100644 --- a/drivers/ntb/hw/mscc/ntb_hw_switchtec.c +++ b/drivers/ntb/hw/mscc/ntb_hw_switchtec.c @@ -19,6 +19,7 @@ #include #include #include +#include MODULE_DESCRIPTION("Microsemi Switchtec(tm) NTB Driver"); MODULE_VERSION("0.1"); @@ -1487,7 +1488,7 @@ static int switchtec_ntb_add(struct device *dev, stdev->sndev = NULL; - if (stdev->pdev->class != MICROSEMI_NTB_CLASSCODE) + if (stdev->pdev->class != (PCI_CLASS_BRIDGE_OTHER << 8)) return -ENODEV; sndev = kzalloc_node(sizeof(*sndev), GFP_KERNEL, dev_to_node(dev)); diff --git a/drivers/pci/switch/switchtec.c b/drivers/pci/switch/switchtec.c index 47cd0c0..07a03b9 100644 --- a/drivers/pci/switch/switchtec.c +++ b/drivers/pci/switch/switchtec.c @@ -1,4 +1,3 @@ -// SPDX-License-Identifier: GPL-2.0 /* * Microsemi Switchtec(tm) PCIe Management Driver * Copyright (c) 2017, Microsemi Corporation @@ -641,7 +640,7 @@ static int ioctl_event_summary(struct switchtec_dev *stdev, for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) { reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id); - if (reg != MICROSEMI_VENDOR_ID) + if (reg != PCI_VENDOR_ID_MICROSEMI) break; reg = ioread32(&stdev->mmio_pff_csr[i].pff_event_summary); @@ -1203,7 +1202,7 @@ static void init_pff(struct switchtec_dev *stdev) for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) { reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id); - if (reg != MICROSEMI_VENDOR_ID) + if (reg != PCI_VENDOR_ID_MICROSEMI) break; } @@ -1267,7 +1266,7 @@ static int switchtec_pci_probe(struct pci_dev *pdev, struct switchtec_dev *stdev; int rc; - if (pdev->class == MICROSEMI_NTB_CLASSCODE) + if (pdev->class == (PCI_CLASS_BRIDGE_OTHER << 8)) request_module_nowait("ntb_hw_switchtec"); stdev = stdev_create(pdev); @@ -1321,19 +1320,19 @@ static void switchtec_pci_remove(struct pci_dev *pdev) #define SWITCHTEC_PCI_DEVICE(device_id) \ { \ - .vendor = MICROSEMI_VENDOR_ID, \ + .vendor = PCI_VENDOR_ID_MICROSEMI, \ .device = device_id, \ .subvendor = PCI_ANY_ID, \ .subdevice = PCI_ANY_ID, \ - .class = MICROSEMI_MGMT_CLASSCODE, \ + .class = (PCI_CLASS_MEMORY_OTHER << 8), \ .class_mask = 0xFFFFFFFF, \ }, \ { \ - .vendor = MICROSEMI_VENDOR_ID, \ + .vendor = PCI_VENDOR_ID_MICROSEMI, \ .device = device_id, \ .subvendor = PCI_ANY_ID, \ .subdevice = PCI_ANY_ID, \ - .class = MICROSEMI_NTB_CLASSCODE, \ + .class = (PCI_CLASS_BRIDGE_OTHER << 8), \ .class_mask = 0xFFFFFFFF, \ } diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index cc608fc5..7b04ca95 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -3073,4 +3073,36 @@ #define PCI_VENDOR_ID_OCZ 0x1b85 +#define PCI_VENDOR_ID_MICROSEMI 0x11f8 +#define PCI_DEVICE_ID_MICROSEMI_PFX24XG3 0x8531 +#define PCI_DEVICE_ID_MICROSEMI_PFX32XG3 0x8532 +#define PCI_DEVICE_ID_MICROSEMI_PFX48XG3 0x8533 +#define PCI_DEVICE_ID_MICROSEMI_PFX64XG3 0x8534 +#define PCI_DEVICE_ID_MICROSEMI_PFX80XG3 0x8535 +#define PCI_DEVICE_ID_MICROSEMI_PFX96XG3 0x8536 +#define PCI_DEVICE_ID_MICROSEMI_PSX24XG3 0x8541 +#define PCI_DEVICE_ID_MICROSEMI_PSX32XG3 0x8542 +#define PCI_DEVICE_ID_MICROSEMI_PSX48XG3 0x8543 +#define PCI_DEVICE_ID_MICROSEMI_PSX64XG3 0x8544 +#define PCI_DEVICE_ID_MICROSEMI_PSX80XG3 0x8545 +#define PCI_DEVICE_ID_MICROSEMI_PSX96XG3 0x8546 +#define PCI_DEVICE_ID_MICROSEMI_PAX24XG3 0x8551 +#define PCI_DEVICE_ID_MICROSEMI_PAX32XG3 0x8552 +#define PCI_DEVICE_ID_MICROSEMI_PAX48XG3 0x8553 +#define PCI_DEVICE_ID_MICROSEMI_PAX64XG3 0x8554 +#define PCI_DEVICE_ID_MICROSEMI_PAX80XG3 0x8555 +#define PCI_DEVICE_ID_MICROSEMI_PAX96XG3 0x8556 +#define PCI_DEVICE_ID_MICROSEMI_PFXL24XG3 0x8561 +#define PCI_DEVICE_ID_MICROSEMI_PFXL32XG3 0x8562 +#define PCI_DEVICE_ID_MICROSEMI_PFXL48XG3 0x8563 +#define PCI_DEVICE_ID_MICROSEMI_PFXL64XG3 0x8564 +#define PCI_DEVICE_ID_MICROSEMI_PFXL80XG3 0x8565 +#define PCI_DEVICE_ID_MICROSEMI_PFXL96XG3 0x8566 +#define PCI_DEVICE_ID_MICROSEMI_PFXI24XG3 0x8571 +#define PCI_DEVICE_ID_MICROSEMI_PFXI32XG3 0x8572 +#define PCI_DEVICE_ID_MICROSEMI_PFXI48XG3 0x8573 +#define PCI_DEVICE_ID_MICROSEMI_PFXI64XG3 0x8574 +#define PCI_DEVICE_ID_MICROSEMI_PFXI80XG3 0x8575 +#define PCI_DEVICE_ID_MICROSEMI_PFXI96XG3 0x8576 + #endif /* _LINUX_PCI_IDS_H */ diff --git a/include/linux/switchtec.h b/include/linux/switchtec.h index ec93e93..ab400af 100644 --- a/include/linux/switchtec.h +++ b/include/linux/switchtec.h @@ -19,10 +19,6 @@ #include #include -#define MICROSEMI_VENDOR_ID 0x11f8 -#define MICROSEMI_NTB_CLASSCODE 0x068000 -#define MICROSEMI_MGMT_CLASSCODE 0x058000 - #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024 #define SWITCHTEC_MAX_PFF_CSR 48