From patchwork Mon Oct 30 04:19:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831869 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQLvL3GYMz9t3v for ; Mon, 30 Oct 2017 15:23:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751996AbdJ3EXY (ORCPT ); Mon, 30 Oct 2017 00:23:24 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:16084 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751304AbdJ3EXX (ORCPT ); Mon, 30 Oct 2017 00:23:23 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 29 Oct 2017 21:22:34 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 29 Oct 2017 21:23:09 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 29 Oct 2017 21:23:09 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:21:19 +0000 Received: from HQMAIL102.nvidia.com (172.18.146.10) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 30 Oct 2017 04:21:18 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 30 Oct 2017 04:21:18 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 29 Oct 2017 21:21:18 -0700 From: Manikanta Maddireddy To: , , , CC: , , , Manikanta Maddireddy Subject: [PATCH V2 12/12] PCI: tegra: Update flow control threshold in Tegra210 Date: Mon, 30 Oct 2017 09:49:03 +0530 Message-ID: <1509337143-25963-13-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> References: <1509337143-25963-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Recommended update FC threshold in Tegra210 is 0x60 for best performance of x1 link. Setting this to 0x60 provides the best balance between number of UpdateFC and read data sent over the link. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index afde9bfb867f..1adf9332560a 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -221,6 +221,7 @@ #define RP_VEND_XP_OPPORTUNISTIC_ACK (1 << 27) #define RP_VEND_XP_OPPORTUNISTIC_UPDATEFC (1 << 28) #define RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK (0xff << 18) +#define RP_VEND_XP_UPDATE_FC_THRESHOLD_T210 (0x60 << 18) #define RP_VEND_CTL0 0xf44 #define RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK (0xf << 12) @@ -321,6 +322,7 @@ struct tegra_pcie_soc { bool update_clamp_threshold; bool RAW_violation_fixup; bool program_deskew_time; + bool updateFC_threshold; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -2229,6 +2231,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port) value |= RP_VEND_CTL0_DSK_RST_PULSE_WIDTH; writel(value, port->base + RP_VEND_CTL0); } + + if (soc->updateFC_threshold) { + value = readl(port->base + RP_VEND_XP); + value &= ~RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK; + value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_T210; + writel(value, port->base + RP_VEND_XP); + } } /* * FIXME: If there are no PCIe cards attached, then calling this function @@ -2368,6 +2377,7 @@ static const struct tegra_pcie_soc tegra20_pcie = { .update_clamp_threshold = false, .RAW_violation_fixup = false, .program_deskew_time = false, + .updateFC_threshold = false, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2388,6 +2398,7 @@ static const struct tegra_pcie_soc tegra30_pcie = { .update_clamp_threshold = false, .RAW_violation_fixup = false, .program_deskew_time = false, + .updateFC_threshold = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2407,6 +2418,7 @@ static const struct tegra_pcie_soc tegra124_pcie = { .update_clamp_threshold = true, .RAW_violation_fixup = true, .program_deskew_time = false, + .updateFC_threshold = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2434,6 +2446,7 @@ static const struct tegra_pcie_soc tegra210_pcie = { .update_clamp_threshold = true, .RAW_violation_fixup = false, .program_deskew_time = true, + .updateFC_threshold = true, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2454,6 +2467,7 @@ static const struct tegra_pcie_soc tegra186_pcie = { .update_clamp_threshold = false, .RAW_violation_fixup = false, .program_deskew_time = false, + .updateFC_threshold = false, }; static const struct of_device_id tegra_pcie_of_match[] = {