From patchwork Fri Oct 27 19:29:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 831459 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yNv9s6XQLz9t4b for ; Sat, 28 Oct 2017 06:30:57 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932293AbdJ0Taz (ORCPT ); Fri, 27 Oct 2017 15:30:55 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19638 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932176AbdJ0Taz (ORCPT ); Fri, 27 Oct 2017 15:30:55 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 27 Oct 2017 12:30:28 -0700 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 27 Oct 2017 12:30:38 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 27 Oct 2017 12:30:38 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 27 Oct 2017 19:30:24 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 27 Oct 2017 19:30:23 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Fri, 27 Oct 2017 19:30:23 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 27 Oct 2017 12:30:23 -0700 From: Manikanta Maddireddy To: , , CC: , , , , Manikanta Maddireddy Subject: [PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed Date: Sat, 28 Oct 2017 00:59:20 +0530 Message-ID: <1509132569-9398-4-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com> References: <1509132569-9398-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra124, 132, 210 and 186 supports Gen2 link speed. After the link is up in Gen1, set target link speed as Gen2 and retrain link. Link switches to Gen2 speed if Gen2 capable end point is connected, else link stays in Gen1. Signed-off-by: Manikanta Maddireddy --- drivers/pci/host/pci-tegra.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 2c64eb6cc3cc..15df60e13a14 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -232,6 +232,8 @@ #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */ #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ +#define LINK_RETRAIN_TIMEOUT HZ + struct tegra_msi { struct msi_controller chip; DECLARE_BITMAP(used, INT_PCI_MSI_NR); @@ -2133,6 +2135,42 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie) } } +static void tegra_pcie_change_link_speed(struct tegra_pcie *pcie, + struct pci_dev *pci_dev) +{ + struct device *dev = pcie->dev; + unsigned long start_jiffies; + unsigned short val; + + /* Skip if the current device is not a root port */ + if (pci_pcie_type(pci_dev) != PCI_EXP_TYPE_ROOT_PORT) + return; + + pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL2, &val); + val &= ~PCI_EXP_LNKSTA_CLS; + val |= PCI_EXP_LNKSTA_CLS_5_0GB; + pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL2, val); + + /* Retrain the link */ + pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &val); + val |= PCI_EXP_LNKCTL_RL; + pcie_capability_write_word(pci_dev, PCI_EXP_LNKCTL, val); + + start_jiffies = jiffies; + for (;;) { + pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &val); + if (!(val & PCI_EXP_LNKSTA_LT)) + break; + if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) + break; + usleep_range(2000, 3000); + } + + if (val & PCI_EXP_LNKSTA_LT) + dev_err(dev, "link retrain of PCIe slot %u failed\n", + PCI_SLOT(pci_dev->devfn)); +} + static const struct tegra_pcie_soc tegra20_pcie = { .num_ports = 2, .msi_base_shift = 0, @@ -2334,6 +2372,7 @@ static int tegra_pcie_probe(struct platform_device *pdev) struct pci_host_bridge *host; struct tegra_pcie *pcie; struct pci_bus *child; + struct pci_dev *pci_dev = NULL; int err; host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); @@ -2399,6 +2438,9 @@ static int tegra_pcie_probe(struct platform_device *pdev) pci_bus_add_devices(host->bus); + for_each_pci_dev(pci_dev) + tegra_pcie_change_link_speed(pcie, pci_dev); + if (IS_ENABLED(CONFIG_DEBUG_FS)) { err = tegra_pcie_debugfs_init(pcie); if (err < 0)