From patchwork Wed Jun 7 11:36:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Schoefegger X-Patchwork-Id: 772368 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wjRNG5wbDz9sDb for ; Wed, 7 Jun 2017 21:36:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751672AbdFGLgd (ORCPT ); Wed, 7 Jun 2017 07:36:33 -0400 Received: from mail.ginzinger.com ([31.193.165.229]:32400 "EHLO mail.ginzinger.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751651AbdFGLgb (ORCPT ); Wed, 7 Jun 2017 07:36:31 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.ginzinger.com (Postfix) with ESMTP id 36177A79; Wed, 7 Jun 2017 13:36:23 +0200 (CEST) X-Virus-Scanned: by amavisd-new-2.10.1 (20141025) (Debian) at ginzinger.com Received: from mail.ginzinger.com ([127.0.0.1]) by localhost (mail.ginzinger.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id wHZyJQHvFIDH; Wed, 7 Jun 2017 13:36:22 +0200 (CEST) Received: from mail.ginzinger.com (unknown [10.1.1.201]) by mail.ginzinger.com (Postfix) with ESMTPS id 080A1A77; Wed, 7 Jun 2017 13:36:22 +0200 (CEST) Received: from en-pc05.buero.ginzinger.com (10.2.1.54) by exc2.buero.ginzinger.com (10.1.1.201) with Microsoft SMTP Server (TLS) id 14.3.339.0; Wed, 7 Jun 2017 13:36:27 +0200 From: Stefan Schoefegger To: CC: Stefan Schoefegger , Bjorn Helgaas , Richard Zhu , Lucas Stach , Kishon Vijay Abraham I , Jingoo Han , Arnd Bergmann , open list , "moderated list:PCI DRIVER FOR IMX6" Subject: [PATCH v2 1/1] PCI: imx6: Add pcie compliance test option Date: Wed, 7 Jun 2017 13:36:11 +0200 Message-ID: <1496835374-13053-1-git-send-email-stefan.schoefegger@ginzinger.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1472121518-9340-1-git-send-email-stefan.schoefegger@ginzinger.com> References: <1472121518-9340-1-git-send-email-stefan.schoefegger@ginzinger.com> MIME-Version: 1.0 X-Originating-IP: [10.2.1.54] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Link speed must not be limited to gen1 during link test for compliance tests Signed-off-by: Stefan Schoefegger --- Changes since v1: - pci-imx6.c moved to dwc directory drivers/pci/dwc/Kconfig | 10 ++++++++++ drivers/pci/dwc/pci-imx6.c | 21 ++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index b7e15526d676..b6e9ced5a45d 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -77,6 +77,16 @@ config PCI_IMX6 select PCIEPORTBUS select PCIE_DW_HOST +config PCI_IMX6_COMPLIANCE_TEST + bool "Enable pcie compliance tests on imx6" + depends on PCI_IMX6 + default n + help + Enables support for pcie compliance test on FSL iMX SoCs. + The link speed wouldn't be limited to gen1 when enabled. + Enable only during compliance tests, otherwise + link detection will fail on some peripherals. + config PCIE_SPEAR13XX bool "STMicroelectronics SPEAr PCIe controller" depends on PCI diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c index 19a289b8cc94..b0fbe52e25b0 100644 --- a/drivers/pci/dwc/pci-imx6.c +++ b/drivers/pci/dwc/pci-imx6.c @@ -533,15 +533,18 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) u32 tmp; int ret; - /* - * Force Gen1 operation when starting the link. In case the link is - * started in Gen2 mode, there is a possibility the devices on the - * bus will not be detected at all. This happens with PCIe switches. - */ - tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); - tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; - tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; - dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); + if (!IS_ENABLED(CONFIG_PCI_IMX6_COMPLIANCE_TEST)) { + /* + * Force Gen1 operation when starting the link. In case the + * link is started in Gen2 mode, there is a possibility the + * devices on the bus will not be detected at all. This + * happens with PCIe switches. + */ + tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); + tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; + tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; + dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); + } /* Start LTSSM. */ if (imx6_pcie->variant == IMX7D)