From patchwork Fri Sep 23 00:50:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajat Jain X-Patchwork-Id: 673763 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sgFDY6v3xz9s4x for ; Fri, 23 Sep 2016 10:51:41 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=bIrHfBux; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934619AbcIWAvk (ORCPT ); Thu, 22 Sep 2016 20:51:40 -0400 Received: from mail-pf0-f171.google.com ([209.85.192.171]:34316 "EHLO mail-pf0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754131AbcIWAvj (ORCPT ); Thu, 22 Sep 2016 20:51:39 -0400 Received: by mail-pf0-f171.google.com with SMTP id p64so35908531pfb.1 for ; Thu, 22 Sep 2016 17:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wEePh5mgHtYjabtvwexwd74I/UUyES78QSLc/TdEI+c=; b=bIrHfBuxEL40azT2v4dh4LIf0I/HzP0GsecRKngDDYV6OPLv64U82v7JRJqgCo9VkZ fy3ENWGMx9MrxP5BTyAKVzzfMuMUL1SLoTbCeAD1FPvYo7oIgYTiFt3NfWlgY2AGInVe CHuSvE42yvcUj4BPHhF20wGbCzyAKassT2TnsYO/OPPXuSWlTtBzUoVtcHRlC5WwKDpE og19wsbenB2/A+ZT9MZcijiHn3ABxgqg/J0DkufPerjrk414hgSIbhcPQ7l10RR/UfD6 47SL2Ah8LSFssmM2WlVwaL2epoM6UKMYLwdnk2xd66+w9YxSiPqKr8PIwwjodgHuGYHC FOsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wEePh5mgHtYjabtvwexwd74I/UUyES78QSLc/TdEI+c=; b=FrhKhTZ5V8dS7kZPSAZSUxvTER2X2dthznulUYdVLGQBcgTiKwASur9ee5ClMjtutD VddCWy1PaPmsqjhxF6hte5tTdoKxszgixlVixwqJul/tTP4UdYwzLr8JtjsZL9QsyZsK hw7dyFFQiYjJabZ/IxgmFtGHV12Kn5R4j1aRJ7zGu1VL1KK7o60Z1DakwsqJoYG68LF4 9Kp2hSMRo6O+kYW8syqFgTXquwZeC5rT/CtJl3hluVyQzRv7fUzBsCk7pbtn1Ok8ehN2 nlTmh/vZ66sa5hnPM9rLGkpkvZS9F8JW1x0T6TQGxhGBXRzEbBLK2EKVS7S3X/ehUD8M 5Gtg== X-Gm-Message-State: AE9vXwPyzDmJDgb3+gAepWw81vHE9CkrL/yQiOvRZ0Ejtg7H+EiGGg5HfJTiEkfTmUvi/zc9 X-Received: by 10.98.47.132 with SMTP id v126mr7951598pfv.152.1474591898077; Thu, 22 Sep 2016 17:51:38 -0700 (PDT) Received: from rajat.mtv.corp.google.com ([172.22.64.13]) by smtp.gmail.com with ESMTPSA id u1sm6605808pfb.62.2016.09.22.17.51.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 Sep 2016 17:51:37 -0700 (PDT) From: Rajat Jain To: linux-pci@vger.kernel.org, Bjorn Helgaas , Shawn Lin , Jeffy Chen , Wenrui Li , Brian Norris Cc: rajatxjain@gmail.com, Rajat Jain Subject: [PATCH v3] PCI: rockchip: Increase the Max Credit update interval. Date: Thu, 22 Sep 2016 17:50:42 -0700 Message-Id: <1474591842-27836-1-git-send-email-rajatja@google.com> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This increases the likelihood of link state to automatically go to L1 and save some power. The default credit update interval of 7.5 us results in the rootport sending UpdateFC-P and UpdateFC-NP packets too often, thus resulting in the link never going to L1, and always staying in L0/L0s. The value 24 us was chosen after some experiments and peeking over the PCIe bus to see that we do enter L1 substate when there is not enough traffic on the PCIe bus. Signed-off-by: Rajat Jain Acked-by: Shawn Lin --- v3: Fix the commit message. v2: Use the link bandwidth change irq to program the register. drivers/pci/host/pcie-rockchip.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index c3593e6..99e700f 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -95,6 +95,11 @@ #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1 +#define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020) +#define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000 +#define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16 +#define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \ + (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT) #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c) #define PCIE_CORE_INT_PRFPE BIT(0) #define PCIE_CORE_INT_CRFPE BIT(1) @@ -224,6 +229,17 @@ static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); } +static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip) +{ + u32 val; + + /* Update Tx credit maximum update interval */ + val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1); + val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK; + val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */ + rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1); +} + static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip, struct pci_bus *bus, int dev) { @@ -597,6 +613,7 @@ static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg) rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS); } else if (reg & PCIE_CLIENT_INT_PHY) { dev_dbg(dev, "phy link changes\n"); + rockchip_pcie_update_txcredit_mui(rockchip); rockchip_pcie_clr_bw_int(rockchip); }