From patchwork Thu Sep 22 21:00:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajat Jain X-Patchwork-Id: 673709 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sg85v0nJqz9t1C for ; Fri, 23 Sep 2016 07:00:34 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b=dVIc6Ra0; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964817AbcIVVAd (ORCPT ); Thu, 22 Sep 2016 17:00:33 -0400 Received: from mail-pa0-f51.google.com ([209.85.220.51]:35300 "EHLO mail-pa0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964901AbcIVVAc (ORCPT ); Thu, 22 Sep 2016 17:00:32 -0400 Received: by mail-pa0-f51.google.com with SMTP id oz2so32700711pac.2 for ; Thu, 22 Sep 2016 14:00:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=LaAvZyJxuZLAd3ua4hugqjA2gVRtolxovUYBpgLNBcY=; b=dVIc6Ra0BJZ6MGnq1bmx74n2nG9owdmFaMSDucPPQR49UcpWG59BN6Eg01tabX9D3u /poutsUj1mvyyP/bHztmdTkLisQAvJ1phe5AfZu8lhgz7jWDCr4SWZAsgoFwBwq2NVMz oB+ckq06gSW4Oxd6bmCxIPvV8aEVugTsx9Q/c/i98m/+uLUqlJACkpWo9EUNYXKln9jk MRopTM8uCEI9DCoL22xbY00rWZi6wEh/Vi73fGmQh1+D5wS638vugd7jEkkE0XavYaM0 vF00etQ+DlHPly8KMv5ml6wnfHtPEOOfldD0oGPiD0FBkf5cX4LCdiM3RcQksWorgkR3 m6iA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=LaAvZyJxuZLAd3ua4hugqjA2gVRtolxovUYBpgLNBcY=; b=S03P1z0u0vUjlh8ZfaZdhDOXfOFs3wBefZtj6zRc+gPM0QNURBHhixLQArlq47gkCB ysY2vbNC6ZXu6Oyhqe/IUc0n9kEM5EVk+3rQ6+fiQ+U6CR9tiEZ+tE+xrfiFSw1zgOWb /pGOgSL/v9exTNuvD0FHk35Vmglk/Wv7mGR2pC1dBehMSrf3BKg7e6icXU8PlpIDE77W JbwofCXJ2wVrFYfCPEiYb4vXDvWQwCKL+4eDxTM290VPmxQKUi6Bh0xnZ2hUb2qfL5dq MfVYQ+/LIreG0JgZND93KV/5PKghyNaCbHlPqARxuSGarrRmDFzb5G0FGaXT4nNQA9GL De0w== X-Gm-Message-State: AE9vXwPuGkCGfqJIOrrvU5vgQGIyzD/xRhgffwM56Yd3Wr/w9vcVlIvcconG3fSV+TCL2j33 X-Received: by 10.66.120.69 with SMTP id la5mr6703047pab.65.1474578031814; Thu, 22 Sep 2016 14:00:31 -0700 (PDT) Received: from rajat.mtv.corp.google.com ([172.22.64.13]) by smtp.gmail.com with ESMTPSA id d9sm6194566pan.7.2016.09.22.14.00.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 Sep 2016 14:00:31 -0700 (PDT) From: Rajat Jain To: linux-pci@vger.kernel.org, Bjorn Helgaas , Shawn Lin , Jeffy Chen , Wenrui Li , Brian Norris Cc: Rajat Jain Subject: [PATCH] rockchip: Increase the Max Credit update interval. Date: Thu, 22 Sep 2016 14:00:27 -0700 Message-Id: <1474578027-64292-1-git-send-email-rajatja@google.com> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This increases the likelihood of link state to automatically go to L1 and save some power. The default credit update interval of 7.5 us results in the rootport sending UpdateFC packets too often, thus reulting in the link never going to L1, and always staying in L0/L0s. The value 24 us was chosen after some experiments and peeking over the PCIe bus to see that we do enter L1 substate when there is not enough traffic on the PCIe bus. The register value gets lost on a Link speed/width change, and the ideal fix should reprogram this on that event (refer "Link Bandwidth Management Interrupt Enable" & "Link Autonomous Bandwidth Interrupt Enable" in link control reg?). But the rockchip platforms doesn't support hotplug and I've verified that the retraining doesn't work as well, so this should be OK. Signed-off-by: Rajat Jain --- drivers/pci/host/pcie-rockchip.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index c3593e6..e537413 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -95,6 +95,11 @@ #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1 +#define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020) +#define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000 +#define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16 +#define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \ + (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT) #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c) #define PCIE_CORE_INT_PRFPE BIT(0) #define PCIE_CORE_INT_CRFPE BIT(1) @@ -523,6 +528,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) PCIE_CORE_PL_CONF_LANE_MASK); dev_dbg(dev, "current link width is x%d\n", status); + /* Update credit update interval */ + status = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1); + status &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK; + status |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */ + rockchip_pcie_write(rockchip, status, PCIE_CORE_TXCREDIT_CFG1); + rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID, PCIE_RC_CONFIG_VENDOR); rockchip_pcie_write(rockchip,