From patchwork Tue Feb 16 13:53:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Nowicki X-Patchwork-Id: 583410 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8D739140297 for ; Wed, 17 Feb 2016 00:54:31 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=semihalf-com.20150623.gappssmtp.com header.i=@semihalf-com.20150623.gappssmtp.com header.b=FoyrNEjO; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932647AbcBPNy3 (ORCPT ); Tue, 16 Feb 2016 08:54:29 -0500 Received: from mail-wm0-f45.google.com ([74.125.82.45]:36907 "EHLO mail-wm0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932615AbcBPNyR (ORCPT ); Tue, 16 Feb 2016 08:54:17 -0500 Received: by mail-wm0-f45.google.com with SMTP id g62so153833383wme.0 for ; Tue, 16 Feb 2016 05:54:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=d8G1zpF8NM1y4EcLeXLAc7JjMLVgq/yn4sev9yTp3wU=; b=FoyrNEjOpQS0Zv5tglnBKn1/CgY3HsKE9cMIXR/UkYLqynefcy57qfqvL/X5IDQ6vc ENI9Jfr+MZamZjLWhQQxJB5foB2z1H/vfNDMeAmaAuxB61V6Uaoz3aPZQWgQdFNWAW7S xgnboC12bgv45oWgM2hqgrzXRboh2lHtqtPoqhEsWAN35d4RSKbMwErwSjSohQj6OhtS Ylbv/CAmjINkh/MrWVnXQzOs/Lpkj+ZUn+IAkqzuaUx8H26U1+ipJRvrivw3K+krnZ+m di2KoZW15ss2elb6dZuPF6cK7Pi8DoxcKr/saLe/CQE+krWFyoJhRScLMEhEyzYUP3xi ZpLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=d8G1zpF8NM1y4EcLeXLAc7JjMLVgq/yn4sev9yTp3wU=; b=APv4eWNQQ3ewk/v81dVqvBaANaAcc2OWig6nPezgoO6H6AROyTQgewiQSOwnOtt9Bx 7AGJcgSAUWe/WqwvrtGPyHNFPXWMDwZKlrPTsAgUm2b7Sac1vIkmOJnGQe0/KQ9UizQJ gR6/yf6GYI2KB+UfhNV6q0H45652/pdx4hC0JtXN7ABi04dWPeXiod+5+Suh6BkzWHSJ j0oriADsDQkpaJ7bHPbTg+lZ5P+7dH+yq90S5BsnhLSyKQyfjTHbK+1GMpery3k40rmJ y6qnOs71oesHM51xYpvZQ6lnjBnVhxB5tBAog8l2jtBQaunKq07NOEOTRjSCRUhk5eRK 6sVw== X-Gm-Message-State: AG10YOQHB6jeuomp0qyFK8Gj8I5ntYnoSuewoaIZCj0+XJjJbUMreYqGN/wV0UgZIedP1A== X-Received: by 10.194.209.204 with SMTP id mo12mr24865859wjc.69.1455630855539; Tue, 16 Feb 2016 05:54:15 -0800 (PST) Received: from tn-HP-4.semihalf.local ([80.82.22.190]) by smtp.gmail.com with ESMTPSA id q129sm20833462wmd.14.2016.02.16.05.54.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 16 Feb 2016 05:54:15 -0800 (PST) From: Tomasz Nowicki To: helgaas@kernel.org, arnd@arndb.de, will.deacon@arm.com, catalin.marinas@arm.com, rafael@kernel.org, hanjun.guo@linaro.org, Lorenzo.Pieralisi@arm.com, okaya@codeaurora.org, jiang.liu@linux.intel.com, jchandra@broadcom.com, Stefano.Stabellini@eu.citrix.com Cc: robert.richter@caviumnetworks.com, mw@semihalf.com, Liviu.Dudau@arm.com, ddaney@caviumnetworks.com, wangyijing@huawei.com, Suravee.Suthikulpanit@amd.com, msalter@redhat.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org, jcm@redhat.com, Tomasz Nowicki Subject: [PATCH V5 12/15] pci, acpi: Support for ACPI based generic PCI host controller initialization Date: Tue, 16 Feb 2016 14:53:42 +0100 Message-Id: <1455630825-27253-13-git-send-email-tn@semihalf.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455630825-27253-1-git-send-email-tn@semihalf.com> References: <1455630825-27253-1-git-send-email-tn@semihalf.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch is going to implement generic PCI host controller for ACPI world, similar to what pci-host-generic.c driver does for DT world. All such drivers, which we have seen so far, were implemented within arch/ directory since they had some arch assumptions (x86 and ia64). However, they all are doing similar thing, so it makes sense to find some common code and abstract it into the generic driver. This driver aims to initialize PCI host controller without architecture assumptions. It uses MCFG library to manage PCI config space regions properly. Also, it parses _CRS content to find out host bridge's resources (i.e. MEM/IO). As mentioned in Kconfig help section, ACPI_PCI_HOST_GENERIC choice should be made on a per-architecture basis. Signed-off-by: Tomasz Nowicki Signed-off-by: Hanjun Guo Signed-off-by: Suravee Suthikulpanit Signed-off-by: Lorenzo Pieralisi TO: Bjorn Helgaas TO: Rafael J. Wysocki Tested-by: Suravee Suthikulpanit Tested-by: Jeremy Linton Tested-by: Duc Dang Tested-by: Dongdong Liu Tested-by: Hanjun Guo Tested-by: Graeme Gregory Tested-by: Sinan Kaya --- drivers/acpi/Kconfig | 7 +++ drivers/acpi/pci_root.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci-acpi.h | 10 ++-- 3 files changed, 141 insertions(+), 4 deletions(-) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index 183ffa3..1c7f57bd 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -346,6 +346,13 @@ config ACPI_PCI_SLOT i.e., segment/bus/device/function tuples, with physical slots in the system. If you are unsure, say N. +config ACPI_PCI_HOST_GENERIC + bool + help + Select this config option from the architecture Kconfig, + if it is preferred to enable ACPI PCI host controller driver which + has no arch-specific assumptions. + config X86_PM_TIMER bool "Power Management Timer Support" if EXPERT depends on X86 diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 3b284dc..02fd690 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -532,6 +532,134 @@ static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm) } } +#ifdef CONFIG_ACPI_PCI_HOST_GENERIC +static int pci_acpi_setup_mcfg_map(struct acpi_pci_root_info *ci) +{ + struct acpi_pci_root *root = ci->root; + int ret; + + ret = pci_mmconfig_insert(&ci->bridge->dev, root->segment, + root->secondary.start, root->secondary.end, + root->mcfg_addr); + if (ret == -EEXIST) + ret = 0; + + return ret; +} + +static void pci_acpi_teardown_mcfg_map(struct acpi_pci_root_info *ci) +{ + struct acpi_pci_root *root = ci->root; + + pci_mmconfig_delete(root->segment, root->secondary.start, + root->secondary.end); + kfree(ci); +} + +static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) +{ + struct list_head *list = &ci->resources; + struct acpi_device *device = ci->bridge; + struct resource_entry *entry, *tmp; + unsigned long flags; + int ret; + + flags = IORESOURCE_IO | IORESOURCE_MEM; + ret = acpi_dev_get_resources(device, list, + acpi_dev_filter_resource_type_cb, + (void *)flags); + if (ret < 0) { + dev_warn(&device->dev, + "failed to parse _CRS method, error code %d\n", ret); + return ret; + } else if (ret == 0) + dev_dbg(&device->dev, + "no IO and memory resources present in _CRS\n"); + + resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { + struct resource *res = entry->res; + + if (entry->res->flags & IORESOURCE_DISABLED) + resource_list_destroy_entry(entry); + else + res->name = ci->name; + + if (res->flags & IORESOURCE_IO) { + resource_size_t cpu_addr = res->start; + resource_size_t pci_addr = cpu_addr - entry->offset; + resource_size_t length = resource_size(res); + unsigned long port; + + if (pci_register_io_range(cpu_addr, length)) { + resource_list_destroy_entry(entry); + continue; + } + + port = pci_address_to_pio(cpu_addr); + if (port == (unsigned long)-1) { + resource_list_destroy_entry(entry); + continue; + } + + res->start = port; + res->end = port + length - 1; + entry->offset = port - pci_addr; + + if (pci_remap_iospace(res, cpu_addr) < 0) + resource_list_destroy_entry(entry); + } + } + return ret; +} + +static struct acpi_pci_root_ops acpi_pci_root_ops = { + .init_info = pci_acpi_setup_mcfg_map, + .release_info = pci_acpi_teardown_mcfg_map, + .prepare_resources = pci_acpi_root_prepare_resources, +}; + +/* Root bridge scanning */ +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + int node = acpi_get_node(root->device->handle); + int domain = root->segment; + int busnum = root->secondary.start; + struct acpi_pci_root_info *info; + struct pci_bus *bus, *child; + + if (domain && !pci_domains_supported) { + pr_warn("PCI %04x:%02x: multiple domains not supported.\n", + domain, busnum); + return NULL; + } + + info = kzalloc_node(sizeof(*info), GFP_KERNEL, node); + if (!info) { + dev_err(&root->device->dev, + "pci_bus %04x:%02x: ignored (out of memory)\n", + domain, busnum); + return NULL; + } + + acpi_pci_root_ops.pci_ops = pci_mcfg_get_ops(root); + bus = acpi_pci_root_create(root, &acpi_pci_root_ops, info, root); + if (!bus) + return NULL; + + pci_bus_claim_resources(bus); + pci_assign_unassigned_bus_resources(bus); + + /* + * After the PCI-E bus has been walked and all devices discovered, + * configure any settings of the fabric that might be necessary. + */ + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + + return bus; +} +#endif /* CONFIG_ACPI_PCI_HOST_GENERIC */ + static int acpi_pci_root_add(struct acpi_device *device, const struct acpi_device_id *not_used) { diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h index 3dc6a8c..93feb04 100644 --- a/include/linux/pci-acpi.h +++ b/include/linux/pci-acpi.h @@ -123,10 +123,6 @@ struct pci_mmcfg_region { bool hot_added; }; -extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, - phys_addr_t addr); -extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end); - extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); extern struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, int end, u64 addr); @@ -142,10 +138,16 @@ extern struct list_head pci_mmcfg_list; #define PCI_MMCFG_OFFSET(bus, devfn) ((bus) << 20 | (devfn) << 12) #ifdef CONFIG_PCI_MMCONFIG +extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, + phys_addr_t addr); +extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end); extern struct pci_ops *pci_mcfg_get_ops(struct acpi_pci_root *root); extern void __iomem *pci_mcfg_dev_base(struct pci_bus *bus, unsigned int devfn, int offset); #else +static inline int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, + u8 end, phys_addr_t addr) { return 0; } +static inline int pci_mmconfig_delete(u16 seg, u8 start, u8 end) { return 0; } static inline struct pci_ops *pci_mcfg_get_ops(struct acpi_pci_root *root) { return NULL; } static inline void __iomem *pci_mcfg_dev_base(struct pci_bus *bus,