From patchwork Thu Feb 4 16:10:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 579014 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 92257140C49 for ; Fri, 5 Feb 2016 03:11:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964947AbcBDQLM (ORCPT ); Thu, 4 Feb 2016 11:11:12 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:11214 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965006AbcBDQLL (ORCPT ); Thu, 4 Feb 2016 11:11:11 -0500 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Websense Email Security Gateway with ESMTPS id 602856718BF67; Thu, 4 Feb 2016 16:11:06 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by HHMAIL01.hh.imgtec.org (10.100.10.19) with Microsoft SMTP Server (TLS) id 14.3.266.1; Thu, 4 Feb 2016 16:11:09 +0000 Received: from localhost (10.100.200.26) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Thu, 4 Feb 2016 16:11:08 +0000 From: Paul Burton To: CC: Bharat Kumar Gogada , Michal Simek , Ravikiran Gummaluri , "Paul Burton" , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Jiang Liu , "Lorenzo Pieralisi" , Grygorii Strashko , Russell Joyce , "Bjorn Helgaas" , , Rob Herring , , Thomas Gleixner , Jingoo Han , Subject: [PATCH v3 2/6] PCI: xilinx: Unify INTx & MSI interrupt FIFO decode Date: Thu, 4 Feb 2016 16:10:09 +0000 Message-ID: <1454602213-967-3-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1454602213-967-1-git-send-email-paul.burton@imgtec.com> References: <1454602213-967-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.26] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org When decoding either an INTx or MSI interrupt, the driver has no way to know which it will pull out of the interrupt FIFO. If both were pending then this would lead to either the interrupt being handled incorrectly (MSI interrupt treated as INTx) or not at all (INTx interrupt dropped by MSI path). Unify the reading of the interrupt FIFO & act according to the type of interrupt actually read. Signed-off-by: Paul Burton Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver") --- Changes in v3: - Split out from Boston patchset. Changes in v2: - Add Fixes tag. drivers/pci/host/pcie-xilinx.c | 47 +++++++++++++----------------------------- 1 file changed, 14 insertions(+), 33 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 1490bd1..afdfb09 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -397,7 +397,7 @@ static const struct irq_domain_ops intx_domain_ops = { static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) { struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data; - u32 val, mask, status, msi_data; + u32 val, mask, status; /* Read interrupt decode and mask registers */ val = pcie_read(port, XILINX_PCIE_REG_IDR); @@ -437,8 +437,8 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) xilinx_pcie_clear_err_interrupts(port); } - if (status & XILINX_PCIE_INTR_INTX) { - /* INTx interrupt received */ + if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) { + /* Interrupt received */ val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); /* Check whether interrupt valid */ @@ -447,41 +447,22 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) return IRQ_HANDLED; } - if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) { - /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); - - /* Handle INTx Interrupt */ + if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { + irq = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & + XILINX_PCIE_RPIFR2_MSG_DATA; + } else { val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >> XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1; - generic_handle_irq(irq_find_mapping(port->irq_domain, - val)); + irq = irq_find_mapping(port->irq_domain, val); } - } - if (status & XILINX_PCIE_INTR_MSI) { - /* MSI Interrupt */ - val = pcie_read(port, XILINX_PCIE_REG_RPIFR1); + /* Clear interrupt FIFO register 1 */ + pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, + XILINX_PCIE_REG_RPIFR1); - if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { - dev_warn(port->dev, "RP Intr FIFO1 read error\n"); - return IRQ_HANDLED; - } - - if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { - msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) & - XILINX_PCIE_RPIFR2_MSG_DATA; - - /* Clear interrupt FIFO register 1 */ - pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK, - XILINX_PCIE_REG_RPIFR1); - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - /* Handle MSI Interrupt */ - generic_handle_irq(msi_data); - } - } + if (IS_ENABLED(CONFIG_PCI_MSI) || + !(val & XILINX_PCIE_RPIFR1_MSI_INTR)) + generic_handle_irq(irq); } if (status & XILINX_PCIE_INTR_SLV_UNSUPP)