From patchwork Wed Feb 3 11:30:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Burton X-Patchwork-Id: 577867 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 01E5414033B for ; Wed, 3 Feb 2016 22:50:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753705AbcBCLck (ORCPT ); Wed, 3 Feb 2016 06:32:40 -0500 Received: from mailapp01.imgtec.com ([195.59.15.196]:58233 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756102AbcBCLch (ORCPT ); Wed, 3 Feb 2016 06:32:37 -0500 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Websense Email Security Gateway with ESMTPS id 1A9CDA5F77E; Wed, 3 Feb 2016 11:32:33 +0000 (GMT) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.266.1; Wed, 3 Feb 2016 11:32:34 +0000 Received: from localhost (10.100.200.105) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Wed, 3 Feb 2016 11:32:34 +0000 From: Paul Burton To: , Ralf Baechle CC: Paul Burton , =?UTF-8?q?S=C3=B6ren=20Brinkmann?= , Michal Simek , "Jiang Liu" , Lorenzo Pieralisi , Grygorii Strashko , Rob Herring , Bjorn Helgaas , , Russell Joyce , , Thomas Gleixner , "Jingoo Han" , Subject: [PATCH v2 06/15] PCI: xilinx: Always clear interrupt decode register Date: Wed, 3 Feb 2016 11:30:36 +0000 Message-ID: <1454499045-5020-7-git-send-email-paul.burton@imgtec.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> References: <1454499045-5020-1-git-send-email-paul.burton@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.200.105] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org If an MSI or INTx interrupt is incorrectly triggered with an empty FIFO then xilinx_pcie_intr_handler will print a warning & skip further processing. However it did not clear the interrupt in the decode register, so the same INTX or MSI interrupt would trigger again immediately even though the FIFO is still empty. Clear the interrupt in the decode register to avoid that situation. Signed-off-by: Paul Burton Fixes: 8961def56845 ("PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver") --- Changes in v2: - Add Fixes tag. drivers/pci/host/pcie-xilinx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index afdfb09..1eb74a2 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -444,7 +444,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) /* Check whether interrupt valid */ if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) { dev_warn(port->dev, "RP Intr FIFO1 read error\n"); - return IRQ_HANDLED; + goto out; } if (val & XILINX_PCIE_RPIFR1_MSI_INTR) { @@ -492,6 +492,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data) if (status & XILINX_PCIE_INTR_MST_ERRP) dev_warn(port->dev, "Master error poison\n"); +out: /* Clear the Interrupt Decode register */ pcie_write(port, status, XILINX_PCIE_REG_IDR);