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Mon, 11 Jan 2016 21:27:54 -0800 Received: from [172.23.64.208] (helo=xhdrdevl6.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1aIrUn-0007lJ-Tc; Mon, 11 Jan 2016 21:27:54 -0800 Received: by xhdrdevl6.xilinx.com (Postfix, from userid 45489) id 836B8F2000E; Tue, 12 Jan 2016 10:57:53 +0530 (IST) From: Bharat Kumar Gogada To: , , , , , , , , , , , , , CC: , , , , "Bharat Kumar Gogada" , Ravi Kiran Gummaluri Subject: [PATCH 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver Date: Tue, 12 Jan 2016 10:56:39 +0530 Message-ID: <1452576399-1513-6-git-send-email-bharatku@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1452576399-1513-1-git-send-email-bharatku@xilinx.com> References: <1452576399-1513-1-git-send-email-bharatku@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22058.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.83; 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PCL:0; RULEID:(601004)(2401047)(520078)(5005006)(8121501046)(13017025)(13018025)(13015025)(10201501046)(3002001); SRVR:SN1NAM02HT246; BCL:0; PCL:0; RULEID:; SRVR:SN1NAM02HT246; X-Forefront-PRVS: 081904387B X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2016 05:28:06.5222 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT246 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch does required modifications to microblaze PCI subsystem, to work with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze and Zynq. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri --- Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture. Modified pcibios_align_resource in pci-common.c, as per generic architecuture. Modified pcibios_get_phb_of_node function in pci-common.c, to remove dependency on struct pci_controller. Removed pci_domain_nr in pci-common.c, instead using generic code. Added pcibios_add_device in pci-common.c, as per generic architecuture. Adding Kernel configuration in arch/microblaze as required for generic PCI domains. Added kernel configuration for driver to support Microblaze. --- arch/microblaze/Kconfig | 3 ++ arch/microblaze/pci/pci-common.c | 61 +++++++++++++++------------------------- drivers/pci/host/Kconfig | 2 +- 3 files changed, 27 insertions(+), 39 deletions(-) diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 0bce820..c3702b9 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -271,6 +271,9 @@ config PCI config PCI_DOMAINS def_bool PCI +config PCI_DOMAINS_GENERIC + def_bool PCI_DOMAINS + config PCI_SYSCALL def_bool PCI diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c index ae838ed..bc72856 100644 --- a/arch/microblaze/pci/pci-common.c +++ b/arch/microblaze/pci/pci-common.c @@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t address) } EXPORT_SYMBOL_GPL(pci_address_to_pio); -/* - * Return the domain number for this bus. - */ -int pci_domain_nr(struct pci_bus *bus) -{ - struct pci_controller *hose = pci_bus_to_host(bus); - - return hose->global_number; -} -EXPORT_SYMBOL(pci_domain_nr); - /* This routine is meant to be used early during boot, when the * PCI bus numbers have not yet been assigned, and you need to * issue PCI config cycles to an OF device. @@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus *bus) void pcibios_fixup_bus(struct pci_bus *bus) { - /* When called from the generic PCI probe, read PCI<->PCI bridge - * bases. This is -not- called when generating the PCI tree from - * the OF device-tree. - */ - if (bus->self != NULL) - pci_read_bridge_bases(bus); - - /* Now fixup the bus bus */ - pcibios_setup_bus_self(bus); - - /* Now fixup devices on that bus */ - pcibios_setup_bus_devices(bus); + /* nothing to do */ } EXPORT_SYMBOL(pcibios_fixup_bus); -static int skip_isa_ioresource_align(struct pci_dev *dev) -{ - return 0; -} - /* * We need to avoid collisions with `mirrored' VGA ports * and other strange ISA hardware, so we always want the @@ -899,20 +872,20 @@ static int skip_isa_ioresource_align(struct pci_dev *dev) resource_size_t pcibios_align_resource(void *data, const struct resource *res, resource_size_t size, resource_size_t align) { - struct pci_dev *dev = data; resource_size_t start = res->start; - if (res->flags & IORESOURCE_IO) { - if (skip_isa_ioresource_align(dev)) - return start; - if (start & 0x300) - start = (start + 0x3ff) & ~0x3ff; - } - return start; } EXPORT_SYMBOL(pcibios_align_resource); +int pcibios_add_device(struct pci_dev *dev) +{ + dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); + + return 0; +} +EXPORT_SYMBOL(pcibios_add_device); + /* * Reparent resource children of pr that conflict with res * under res, and make res replace those children. @@ -1335,9 +1308,21 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose, struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) { - struct pci_controller *hose = bus->sysdata; + struct device_node *np; + + for_each_node_by_type(np, "pci") { + const void *prop; + unsigned int bus_min; + + prop = of_get_property(np, "bus-range", NULL); + if (!prop) + continue; + bus_min = be32_to_cpup(prop); + if (bus->number == bus_min) + return np; + } - return of_node_get(hose->dn); + return NULL; } static void pcibios_scan_phb(struct pci_controller *hose) diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index d5e58ba..7c56c2e 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -79,7 +79,7 @@ config PCI_KEYSTONE config PCIE_XILINX bool "Xilinx AXI PCIe host bridge support" - depends on ARCH_ZYNQ + depends on ARCH_ZYNQ || MICROBLAZE help Say 'Y' here if you want kernel to support the Xilinx AXI PCIe Host Bridge driver.