From patchwork Tue Jan 12 05:26:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Kumar Gogada X-Patchwork-Id: 566289 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2B3201402A1 for ; Tue, 12 Jan 2016 16:28:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753107AbcALF2G (ORCPT ); Tue, 12 Jan 2016 00:28:06 -0500 Received: from mail-cys01nam02on0050.outbound.protection.outlook.com ([104.47.37.50]:44896 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750898AbcALF17 (ORCPT ); Tue, 12 Jan 2016 00:27:59 -0500 Received: from CY1NAM02FT013.eop-nam02.prod.protection.outlook.com (10.152.74.55) by CY1NAM02HT012.eop-nam02.prod.protection.outlook.com (10.152.74.250) with Microsoft SMTP Server (TLS) id 15.1.355.15; Tue, 12 Jan 2016 05:27:57 +0000 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; york.ac.uk; dkim=none (message not signed) header.d=none;york.ac.uk; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.100 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.100; helo=xsj-pvapsmtpgw02; Received: from xsj-pvapsmtpgw02 (149.199.60.100) by CY1NAM02FT013.mail.protection.outlook.com (10.152.75.162) with Microsoft SMTP Server (TLS) id 15.1.355.15 via Frontend Transport; Tue, 12 Jan 2016 05:27:56 +0000 Received: from unknown-38-66.xilinx.com ([149.199.38.66]:60158 helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw02 with esmtp (Exim 4.63) (envelope-from ) id 1aIrUp-0004ro-Ju; Mon, 11 Jan 2016 21:27:55 -0800 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1aIrUp-0007lu-Ea; Mon, 11 Jan 2016 21:27:55 -0800 Received: from xsj-pvapsmtp01 (smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u0C5Rq9C016266; Mon, 11 Jan 2016 21:27:53 -0800 Received: from [172.23.64.208] (helo=xhdrdevl6.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1aIrUm-0007lJ-Ls; Mon, 11 Jan 2016 21:27:52 -0800 Received: by xhdrdevl6.xilinx.com (Postfix, from userid 45489) id B4C08F2000E; Tue, 12 Jan 2016 10:57:51 +0530 (IST) From: Bharat Kumar Gogada To: , , , , , , , , , , , , , CC: , , , , "Bharat Kumar Gogada" , Ravi Kiran Gummaluri Subject: [PATCH 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Date: Tue, 12 Jan 2016 10:56:37 +0530 Message-ID: <1452576399-1513-4-git-send-email-bharatku@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1452576399-1513-1-git-send-email-bharatku@xilinx.com> References: <1452576399-1513-1-git-send-email-bharatku@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22058.006 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(2980300002)(438002)(189002)(199003)(36386004)(2201001)(5008740100001)(189998001)(4326007)(42186005)(2950100001)(50466002)(63266004)(50986999)(50226001)(87936001)(103686003)(4001430100002)(19580395003)(47776003)(106466001)(5003940100001)(1220700001)(48376002)(81156007)(36756003)(19580405001)(90966002)(92566002)(11100500001)(1096002)(5001960100002)(229853001)(5001770100001)(107886002)(33646002)(46386002)(6806005)(76176999)(586003)(86362001)(52956003)(2906002)(45336002)(107986001)(921003)(5001870100001)(1121003)(2101003)(83996005); DIR:OUT; SFP:1101; SCL:1; SRVR:CY1NAM02HT012; H:xsj-pvapsmtpgw02; FPR:; SPF:Pass; PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: d8d20049-db26-44ee-9290-08d31b1120f4 X-Exchange-Antispam-Report-Test: UriScan:; BCL:0; PCL:0; RULEID:(8251501002); SRVR:CY1NAM02HT012; UriScan:(192813158149592); X-Microsoft-Antispam-PRVS: <3279367788574e5b98bc528471f996d6@CY1NAM02HT012.eop-nam02.prod.protection.outlook.com> X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(8121501046)(13015025)(5005006)(13018025)(520078)(13017025)(10201501046)(3002001); SRVR:CY1NAM02HT012; BCL:0; PCL:0; RULEID:; SRVR:CY1NAM02HT012; X-Forefront-PRVS: 081904387B X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2016 05:27:56.1758 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1NAM02HT012 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both Zynq and Microblaze Architectures. With these modifications drivers/pci/host/pcie-xilinx.c, will work on both Zynq and Microblaze Architectures. Signed-off-by: Bharat Kumar Gogada Signed-off-by: Ravi Kiran Gummaluri --- Changes: Changed Total number of MSI IRQ count logic according to both architectures. Updated MSI assigning functions accordingly to new count. Modified irq_domain_add_linear with new MSI IRQ count. Added #ifdef to pci_fixup_irqs which are ARM specific API. --- drivers/pci/host/pcie-xilinx.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index 3e3757f..05f6f2e 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -93,6 +93,11 @@ /* Number of MSI IRQs */ #define XILINX_NUM_MSI_IRQS 128 +#ifdef CONFIG_ARM +#define TOT_NR_IRQS XILINX_NUM_MSI_IRQS +#else +#define TOT_NR_IRQS (NR_IRQS + XILINX_NUM_MSI_IRQS) +#endif /** @@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq) */ static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port) { + int irq; int pos; pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS); - if (pos < XILINX_NUM_MSI_IRQS) + irq = pos; +#ifdef CONFIG_MICROBLAZE + irq = XILINX_NUM_MSI_IRQS + pos; +#endif + if (irq < TOT_NR_IRQS) set_bit(pos, msi_irq_in_use); else return -ENOSPC; - return pos; + return irq; } /** @@ -520,7 +530,7 @@ static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port) free_pages(port->msi_pages, 0); - num_irqs = XILINX_NUM_MSI_IRQS; + num_irqs = TOT_NR_IRQS; } else { /* INTx */ num_irqs = 4; @@ -565,7 +575,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port) /* Setup MSI */ if (IS_ENABLED(CONFIG_PCI_MSI)) { port->irq_domain = irq_domain_add_linear(node, - XILINX_NUM_MSI_IRQS, + TOT_NR_IRQS, &msi_domain_ops, &xilinx_pcie_msi_chip); if (!port->irq_domain) { @@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev) #endif pci_scan_child_bus(bus); pci_assign_unassigned_bus_resources(bus); +#ifdef CONFIG_ARM pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); +#endif pci_bus_add_devices(bus); platform_set_drvdata(pdev, port);