From patchwork Fri Dec 18 12:38:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stanimir Varbanov X-Patchwork-Id: 558863 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5CBE114029E for ; Fri, 18 Dec 2015 23:51:16 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b=QECuFB/p; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753201AbbLRMjX (ORCPT ); Fri, 18 Dec 2015 07:39:23 -0500 Received: from mail-wm0-f42.google.com ([74.125.82.42]:38548 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753135AbbLRMjV (ORCPT ); Fri, 18 Dec 2015 07:39:21 -0500 Received: by mail-wm0-f42.google.com with SMTP id l126so63483559wml.1 for ; Fri, 18 Dec 2015 04:39:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uNiOdE91x72CQiQJEr/iqtsJSXqi1RL6SoYUpc7VLZA=; b=QECuFB/pEka8ABiMxoHpNmbeYcwxOhoSKPla/j+p6Uarcmq1/wTb8SnOSnYlp4BXN8 3f2c4UuKmq3mVvaxxiGB55ocZNQHaMkjpKTSSnSzRp6SU1AuStMM3jrlzEXI3+SQtvh7 1gZQSv514ObsE5R+44pg0LvNuq22Kj9KPhXHk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uNiOdE91x72CQiQJEr/iqtsJSXqi1RL6SoYUpc7VLZA=; b=Ka2oyCfRHJDtMPnl1V0JC4ILTtKoihFLI2bwg5kERKJXw5b7t/K1fDqKRW82kxA74K AhB0qOOVkVWpWhb/ezD2e30nSLf/MD1iR/ahnD27XnA0uxmrgMCDHIGSs66hfMI5jr9a Z1bG2mm2sIJub0GQb5B9fLvem65m/VDS1uu8How7TdFufijGQRlruRPITKwD/lSwlJHc GAZ2k0Ev3gaDI+hSF99em0r1WkVUg/R8g9Z406NVK8mcgC3M70tNj+J72dKgpA1m6EtL R91bZqWxDUNBxmpCc8h6/CZrDRjaPQOOzbyJFdZoX9EHLK5s9h5EObtKDa9/5NvusFlX GThQ== X-Gm-Message-State: ALoCoQkLoHqA6x0umERVraVifgIA+hv44NuLezMi0kSI2v0P+lZ9QO2wgZau7ThlyWb5VmmzcSB8Vt95X9e4iRSQtWeN03fP6w== X-Received: by 10.194.133.100 with SMTP id pb4mr4501333wjb.133.1450442360443; Fri, 18 Dec 2015 04:39:20 -0800 (PST) Received: from mms734.qualcomm.mm-sol.com ([37.157.136.206]) by smtp.gmail.com with ESMTPSA id c13sm6521619wmd.14.2015.12.18.04.39.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Dec 2015 04:39:19 -0800 (PST) From: Stanimir Varbanov To: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, Bjorn Helgaas Cc: Srinivas Kandagatla , Russell King , Rob Herring , Rob Herring , Mark Rutland , Pawel Moll , Ian Campbell , Arnd Bergmann , Jingoo Han , Pratyush Anand , Bjorn Andersson , Stanimir Varbanov Subject: [PATCH v5 1/5] PCI: designware: ensure ATU is enabled before IO/conf space accesses Date: Fri, 18 Dec 2015 14:38:55 +0200 Message-Id: <1450442339-18765-2-git-send-email-stanimir.varbanov@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1450442339-18765-1-git-send-email-stanimir.varbanov@linaro.org> References: <1450442339-18765-1-git-send-email-stanimir.varbanov@linaro.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org There is no guarantees that enabling ATU will hit the hardware immediately, and subsequent accesses to configuration / IO spaces are reliable. So fixing this by read back PCIE_ATU_CR2 register just after writing. Without such a fix the PCI device enumeration during kernel boot is not reliable, and reading configuration space for particular PCI device on the bus returns zero aka no device. Signed-off-by: Stanimir Varbanov Acked-by: Pratyush Anand --- drivers/pci/host/pcie-designware.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 02a7452bdf23..7880de63895d 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -154,6 +154,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, int type, u64 cpu_addr, u64 pci_addr, u32 size) { + u32 val; + dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, PCIE_ATU_VIEWPORT); dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE); @@ -164,6 +166,11 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET); dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); + /* + * ensure that the ATU enable has been happaned before accessing + * pci configuration/io spaces through dw_pcie_cfg_[read|write]. + */ + dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val); } static struct irq_chip dw_msi_irq_chip = {