From patchwork Thu Aug 6 04:11:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 504481 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 66BE914075A for ; Thu, 6 Aug 2015 14:13:39 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753918AbbHFENg (ORCPT ); Thu, 6 Aug 2015 00:13:36 -0400 Received: from e23smtp07.au.ibm.com ([202.81.31.140]:50904 "EHLO e23smtp07.au.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753584AbbHFENT (ORCPT ); Thu, 6 Aug 2015 00:13:19 -0400 Received: from /spool/local by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 6 Aug 2015 14:13:15 +1000 X-Helo: d23dlp03.au.ibm.com X-MailFrom: gwshan@linux.vnet.ibm.com X-RcptTo: linux-pci@vger.kernel.org Received: from d23relay08.au.ibm.com (d23relay08.au.ibm.com [9.185.71.33]) by d23dlp03.au.ibm.com (Postfix) with ESMTP id E4002357805E; Thu, 6 Aug 2015 14:13:14 +1000 (EST) Received: from d23av01.au.ibm.com (d23av01.au.ibm.com [9.190.234.96]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t764D1iu60096628; Thu, 6 Aug 2015 14:13:09 +1000 Received: from d23av01.au.ibm.com (localhost [127.0.0.1]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t764CbHR001262; Thu, 6 Aug 2015 14:12:42 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av01.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t764CbqC000629; Thu, 6 Aug 2015 14:12:37 +1000 Received: from bran.ozlabs.ibm.com (unknown [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 09009A0400; Thu, 6 Aug 2015 14:12:04 +1000 (AEST) Received: from gwshan (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id F0090E38F9; Thu, 6 Aug 2015 14:12:03 +1000 (AEST) Received: by gwshan (Postfix, from userid 1000) id D611694222F; Thu, 6 Aug 2015 14:12:03 +1000 (AEST) From: Gavin Shan To: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, benh@kernel.crashing.org, mpe@ellerman.id.au, bhelgaas@google.com, grant.likely@linaro.org, robherring2@gmail.com, panto@antoniou-consulting.com, aik@ozlabs.ru, Gavin Shan Subject: [PATCH v6 25/42] powerpc/powernv: Use PCI slot reset infrastructure Date: Thu, 6 Aug 2015 14:11:30 +1000 Message-Id: <1438834307-26960-26-git-send-email-gwshan@linux.vnet.ibm.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1438834307-26960-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1438834307-26960-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15080604-0025-0000-0000-000001EFA47C Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The skiboot firmware might provide the capability of resetting PCI slot by property "ibm,reset-by-firmware" on the PCI slot associated device node. The patch checks on the property and route the reset to firmware if the property exists. Otherwise, we fail back to the old path as before. Signed-off-by: Gavin Shan --- arch/powerpc/platforms/powernv/eeh-powernv.c | 44 +++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c index 0350dab..7be2ebf 100644 --- a/arch/powerpc/platforms/powernv/eeh-powernv.c +++ b/arch/powerpc/platforms/powernv/eeh-powernv.c @@ -843,7 +843,7 @@ out: return 0; } -static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option) +static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) { struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); struct eeh_dev *edev = pdn_to_eeh_dev(pdn); @@ -894,6 +894,48 @@ static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option) return 0; } +static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) +{ + struct pci_controller *hose; + struct pnv_phb *phb; + struct device_node *dn = pdev ? pci_device_to_OF_node(pdev) : NULL; + uint64_t id = (0x1ul << 60); + uint8_t scope; + int64_t rc; + + /* + * If the firmware can't handle it, we will issue hot reset + * on the secondary bus despite the requested reset type. + */ + if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) + return __pnv_eeh_bridge_reset(pdev, option); + + /* The firmware can handle the request */ + switch (option) { + case EEH_RESET_HOT: + scope = OPAL_RESET_PCI_HOT; + break; + case EEH_RESET_FUNDAMENTAL: + scope = OPAL_RESET_PCI_FUNDAMENTAL; + break; + case EEH_RESET_DEACTIVATE: + return 0; + default: + dev_warn(&pdev->dev, "%s: Unsupported reset %d\n", + __func__, option); + return -EINVAL; + } + + hose = pci_bus_to_host(pdev->bus); + phb = hose->private_data; + id |= (pdev->bus->number << 24) | (pdev->devfn << 16) | phb->opal_id; + rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); + if (rc > 0) + rc = pnv_eeh_poll(id); + + return (rc == OPAL_SUCCESS) ? 0 : -EIO; +} + static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, int pos, u16 mask, bool af_flr_rst) {