From patchwork Wed Jul 8 11:14:18 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 492852 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B9BAE1402AA for ; Wed, 8 Jul 2015 21:19:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758896AbbGHLOr (ORCPT ); Wed, 8 Jul 2015 07:14:47 -0400 Received: from mga11.intel.com ([192.55.52.93]:30312 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758064AbbGHLOo (ORCPT ); Wed, 8 Jul 2015 07:14:44 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 08 Jul 2015 04:14:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,431,1432623600"; d="scan'208";a="520752881" Received: from black.fi.intel.com ([10.237.72.82]) by FMSMGA003.fm.intel.com with ESMTP; 08 Jul 2015 04:14:20 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id DB31E5CC; Wed, 8 Jul 2015 14:14:19 +0300 (EEST) From: Andy Shevchenko To: linux-kernel@vger.kernel.org, Bjorn Helgaas , linux-pci@vger.kernel.org, Thomas Gleixner , Ingo Molnar , x86@kernel.org Cc: Andy Shevchenko Subject: [PATCH v2 2/3] x86/pci/intel_mid_pci: propagate actual return code Date: Wed, 8 Jul 2015 14:14:18 +0300 Message-Id: <1436354059-130135-3-git-send-email-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436354059-130135-1-git-send-email-andriy.shevchenko@linux.intel.com> References: <1436354059-130135-1-git-send-email-andriy.shevchenko@linux.intel.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org mp_map_gsi_to_irq() returns different codes if it fails. intel_mid_pci_irq_enable() hides this under -EBUSY. The patch replaces it by what is actually returned. Signed-off-by: Andy Shevchenko --- arch/x86/pci/intel_mid_pci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c index 5d7f4afe..4739834 100644 --- a/arch/x86/pci/intel_mid_pci.c +++ b/arch/x86/pci/intel_mid_pci.c @@ -212,6 +212,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) { struct irq_alloc_info info; int polarity; + int ret; if (dev->irq_managed && dev->irq > 0) return 0; @@ -232,6 +233,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) } } + /* Set IRQ polarity */ if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER) polarity = 0; /* active high */ else @@ -242,8 +244,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev) * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to * IOAPIC RTE entries, so we just enable RTE for the device. */ - if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0) - return -EBUSY; + ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info); + if (ret < 0) + return ret; dev->irq_managed = 1;