From patchwork Thu Jun 11 12:11:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wan ZongShun X-Patchwork-Id: 483126 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D15891401AB for ; Thu, 11 Jun 2015 22:26:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750825AbbFKM0r (ORCPT ); Thu, 11 Jun 2015 08:26:47 -0400 Received: from mail-bn1bbn0103.outbound.protection.outlook.com ([157.56.111.103]:62512 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753070AbbFKM0p (ORCPT ); Thu, 11 Jun 2015 08:26:45 -0400 X-Greylist: delayed 964 seconds by postgrey-1.27 at vger.kernel.org; Thu, 11 Jun 2015 08:26:44 EDT Received: from BY2PR02CA0060.namprd02.prod.outlook.com (10.141.216.50) by BN1PR02MB070.namprd02.prod.outlook.com (10.242.211.14) with Microsoft SMTP Server (TLS) id 15.1.184.17; Thu, 11 Jun 2015 12:10:58 +0000 Received: from BL2FFO11FD016.protection.gbl (2a01:111:f400:7c09::145) by BY2PR02CA0060.outlook.office365.com (2a01:111:e400:2c40::50) with Microsoft SMTP Server (TLS) id 15.1.190.14 via Frontend Transport; Thu, 11 Jun 2015 12:10:51 +0000 Authentication-Results: spf=none (sender IP is 165.204.84.221) smtp.mailfrom=amd.com; alien8.de; dkim=none (message not signed) header.d=none; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from atltwp01.amd.com (165.204.84.221) by BL2FFO11FD016.mail.protection.outlook.com (10.173.160.224) with Microsoft SMTP Server id 15.1.190.9 via Frontend Transport; Thu, 11 Jun 2015 12:10:51 +0000 X-WSS-ID: 0NPS4I1-07-OXS-02 X-M-MSG: Received: from satlvexedge01.amd.com (satlvexedge01.amd.com [10.177.96.28]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by atltwp01.amd.com (Axway MailGate 5.3.1) with ESMTPS id 228BACAE645; Thu, 11 Jun 2015 08:10:49 -0400 (EDT) Received: from SATLEXDAG01.amd.com (10.181.40.3) by satlvexedge01.amd.com (10.177.96.28) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 11 Jun 2015 07:11:26 -0500 Received: from SCYBEXDAG01.amd.com (10.34.11.11) by SATLEXDAG01.amd.com (10.181.40.3) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 11 Jun 2015 08:10:49 -0400 Received: from zswan-developer.amd.com (10.237.75.59) by SCYBEXDAG01.amd.com (10.34.11.11) with Microsoft SMTP Server id 14.3.195.1; Thu, 11 Jun 2015 20:10:45 +0800 From: Wan ZongShun To: , , , , CC: , , , Wan ZongShun Subject: [PATCH V2 3/3] SDHCI: Change AMD SDHCI quirk application scope Date: Thu, 11 Jun 2015 20:11:47 +0800 Message-ID: <1434024707-6245-3-git-send-email-Vincent.Wan@amd.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1434024707-6245-1-git-send-email-Vincent.Wan@amd.com> References: <1434024707-6245-1-git-send-email-Vincent.Wan@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BL2FFO11FD016; 1:QMt5X7qhOQY13lPFjvGt/PF+f3zkbmrQGyRu+rMtHxGbebT8Hlc22B3IBwxmaTB928Or6zRjUQ96IoZkgKsagUt+6UXShMG7hI6z7ifQCJkmjr3816QXjQx8Ebg2wP9pGljF9/yGnznA85SXmOrCkjIVuJQo0YjmA7E3dI6Ls1YdZkfnKCUNqX6yg3a1sAR71TgqIbRBSDATWYYhuvbhRv1+a72kz9a9P5BFTjc+vfUM1WTZZGeMANGNPOjlcBR1ipzWE3/3FqCeNu+UZrYgIIYEbvjCO7OIN6jaSmZfBKh8reIkip3UZsGZWcIPte8CHV90hxVVNQTepp3cMCoLAA== X-Forefront-Antispam-Report: CIP:165.204.84.221; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(428002)(189002)(199003)(77096005)(5003600100002)(5001770100001)(189998001)(2950100001)(229853001)(53416004)(46102003)(86362001)(77156002)(2201001)(87936001)(62966003)(92566002)(101416001)(76176999)(48376002)(50466002)(50226001)(47776003)(106466001)(36756003)(105586002)(19580405001)(19580395003)(50986999)(217873001); DIR:OUT; SFP:1102; SCL:1; SRVR:BN1PR02MB070; H:atltwp01.amd.com; FPR:; SPF:None; MLV:sfv; MX:1; A:1; LANG:en; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BN1PR02MB070; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(520003)(5005006)(3002001); SRVR:BN1PR02MB070; BCL:0; PCL:0; RULEID:; SRVR:BN1PR02MB070; X-Forefront-PRVS: 0604AFA86B X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2015 12:10:51.4691 (UTC) X-MS-Exchange-CrossTenant-Id: fde4dada-be84-483f-92cc-e026cbee8e96 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=fde4dada-be84-483f-92cc-e026cbee8e96; Ip=[165.204.84.221]; Helo=[atltwp01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN1PR02MB070 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Change this quirk to apply to AMD Carrizo platform. Signed-off-by: Wan ZongShun Tested-by: Nath, Arindam Tested-by: Ramesh, Ramya --- drivers/mmc/host/sdhci-pci.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c index f208f20..94f54d2 100644 --- a/drivers/mmc/host/sdhci-pci.c +++ b/drivers/mmc/host/sdhci-pci.c @@ -724,14 +724,37 @@ static const struct sdhci_pci_fixes sdhci_rtsx = { .probe_slot = rtsx_probe_slot, }; +/*AMD chipset generation*/ +enum amd_chipset_gen { + AMD_CHIPSET_BEFORE_ML, + AMD_CHIPSET_CZ, + AMD_CHIPSET_NL, + AMD_CHIPSET_UNKNOWN, +}; + static int amd_probe(struct sdhci_pci_chip *chip) { struct pci_dev *smbus_dev; + enum amd_chipset_gen gen; smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); + if (smbus_dev) { + gen = AMD_CHIPSET_BEFORE_ML; + } else { + smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); + if (smbus_dev) { + if (smbus_dev->revision < 0x51) + gen = AMD_CHIPSET_CZ; + else + gen = AMD_CHIPSET_NL; + } else { + gen = AMD_CHIPSET_UNKNOWN; + } + } - if (smbus_dev && (smbus_dev->revision < 0x51)) { + if ((gen == AMD_CHIPSET_BEFORE_ML) || (gen == AMD_CHIPSET_CZ)) { chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; }